MOS Processing

As mentioned earlier, the two main semiconducting processes are bipolar and MOS. The most important microelectronic device available from an MOS process is the field-effect or unipolar transistor. There are two main kinds of FETs (see Figure 4.24): the junction field-effect transistor (JFET) and the metal insulator gate field-effect transistor (MISFET).

Both types of transistors, namely, n -channel and p-channel, are available in advanced CMOS or BiCMOS technologies; however, it should be emphasised that the MISFET is an insulated gate control device, whereas JFET is a p-n junction control device. In silicon technology, an insulator is readily available, that is, an oxide for the MISFET, and this transistor is called a MOSFET. Here, we describe the process for making a MOSFET rather than the simpler JFET because of the greater use of MOSFETs in ICs and micro-transducers. Since the 1980s, MOSFETs have tended to be made with polysilicon rather than metal gates because of the better device characteristics (lower parasitic capacitance) and hence we show this process, although it is a slightly more complicated one.

As in the bipolar process, a transistor can be made in a number of different ways, depending on whether high frequency or high power is required. The small-signal planar MOSFET is fabricated using a simple substrate process, and Figure 4.25 summarises this process for an n-type enhancement-mode MOSFET.

Worked Example E4.2: n-type Enhancement-Mode MOSFET

The process starts with taking a p-type single-crystalline silicon wafer as the substrate and growing a thermal oxide layer, followed by the growth of an n-type polysilicon layer. The polysilicon is then patterned (mask 1) using optical lithography to define the polysilicon gate. The polygate is then used as a mask for a deep ion implantation

MONOLITHIC PROCESSING 91

(a)

p-silicon (b)

p-silicon

p-type substrate

-Grow SiO,

Grow polysilicon n-type

(d)

p-silicon

Mask to leave gate opening

Polygate

p-silicon

Ion-implant with poly gate acting as mask

Source 9 DrainGate

Body (0

Etch contact areas through oxide, metalize, and attach source, drain, and gate

Figure 4.25 Basic steps involved with the fabrication of a small-signal planar (long-channel) enhancement-mode n-channel MOSFET

of the two n⁺ regions that form the source and the drain on either side of the gate.

Contacts to the source and drain regions are then opened up by patterning (mask 2) the oxide layer - again with optical lithography. Next, the metal interconnect is formed by the deposition and patterning (mask 3) of a metal layer, such as aluminum, and a final oxide passivation layer that is deposited and patterned (mask 4) to leave just the wire-bonding pads exposed. A p-channel MOSFET is usually made in a CMOS process by depositing an N-Well in the p-type wafer and so it usually takes a minimum of five masks⁹ for a CMOS circuit with additional steps for LOCOS rather than junction isolation.

As in the bipolar process, the properties of the small-signal planar MOSFET are deter-mined by the accuracy of the photolithography. Once again, lateral and vertical transistors can be made, and this is known as a diffused-channel metal oxide semiconductor (DMOS) process. The lateral MOSFET can have a smaller channel¹⁰ and so runs at lower power and higher frequencies, whereas the vertical MOSFET is a power device. Figure 4.26 illustrates the DMOS process used to make a lateral n-channel MOSFET.

9 A sixth mask can be used for threshold implant adjustment.

10 Commonly referred to as a short-channel device.

92 STANDARD MICROELECTRONIC TECHNOLOGIES Channel p-type substrate

Grow SiO,

Grow silicon nitride

Mask for gate

Etch nitride, leaving gate

Mask drain area, overlap gate, implant p-doped channel

Figure 4.26 Basic steps involved with the enhancement-mode n -channel MOSFET

Remove mask, implant whole with n+

Remove nitride

Poly over wafer

Mask and etch poly

Ion-implant with light

Metalize contacts for source, gate, and drain

fabrication of a lateral (short-channel)

Worked Example E4.3: A Lateral n-channel MOSFET

The process begins with the p-type single-crystalline substrate onto which is grown a layer of oxide and then nitride. The nitride is then patterned (mask 1) and etched to leave a nitride gate. Next, the drain area is masked off (mask 2) and the narrow p-type channel is formed by ion implantation. The nitride gate and masked-off drain area are then removed, and another mask (4) is used to define the n+ ion implantation regions of the source and drain. Polysilicon is then grown over the whole wafer and patterned (mask 5) to leave a polygate that extends well over the source n⁺ region and towards the drain. The polygate is then used as a mask for a light n^– ion implantation of a thin channel beneath the oxide. Finally, windows are opened up through the oxide by another lithographic process (mask 6) to the source and drain regions and a metal layer that is deposited and patterned (mask 7) to form the connections to the gate, source, and drain regions.

The DMOS process for the lateral MOSFET leads to a reproducible short-channel device with a high transconductance (see Section 4.3.4), and this process is widely used to make high-speed switching circuitry. Power MOSFETs are made using a vertical DMOS process that is slightly more complicated than the lateral DMOS process. Figure 4.27 shows most of the steps required to make a vertical enhancement-mode n-channel power MOSFET. The process starts with a heavily n+-doped n-type substrate rather than a p-type

MONOLITHIC PROCESSING 93

(a)

Y//////////////L

gate mask Etch oxide

Diffuse p body

n (arsenic) implant

Grow oxide and mask n-type substrate

Grow epitaxy

Grow SiO

Mask and etch

Implant deep p+

and oxidation Deposit photoresist mask and remove photoresist Etch photoresist

Strip photoresist

Gate oxide

Figure 4.27 Basic steps involved with the fabrication of a vertical (short-channel) enhance-ment-mode n -channel power MOSFET

substrate. A thick lightly doped n epi-layer is grown on the wafer and from thereon the steps are shown in Figure 4.27. The vertical configuration produces low channel resistance and hence large currents to flow through the device. Vertical power MOSFETs are used as power drives in actuators, whereas small-signal lateral MOSFETs are used to amplify and condition signals in sensors.

Source

Etch for source contacts and lay source metal