MONOLITHIC MOUNTING

p+ n p* n+ p n'

Sapphire substrate

Figure 4.34 Structure of an SOI CMOS device for a high-speed, low-power IC

Figure 4.35 Proposed structure of a gas-sensitive MOSFET fabricated using SOI technology.

From Udrea and Gardner (1998)

is unaffected (Udrea and Gardner 1998). More details are given in Chapter 15 on the topic of 'smart sensors.'

4.4 MONOLITHIC MOUNTING

There are a number of different technologies that can be used both to package electronic devices and to make circuit interconnections as shown in Figure 4.36. In monolithic mounting, the circuit interconnections have usually been created by the patterning of one or more metallisation layers with, perhaps, some local polysilicon tracks in a CMOS process. Therefore, the mounting process needs both to provide a suitable path for the electrical signals from the single silicon die or chip to the substrate and to attach the die to the substrate. A further consideration is the need to create a suitable path to transfer heat from the chip to the substrate to limit the operating temperature of the 1C.

Figure 4.36 shows the four main technologies that are used to mount a chip that would normally be standard components, such as MOSFET transistors or TTL logic devices, or, a microtransducer or MEMS device that is of particular interest here, such as a temperature IC or electrostatic microactuator.

The choice of monolithic mounting technique has implications not only to the pack-aging cost but also to the basic characteristics of the device. Table 4.6 summarises the

100 STANDARD MICROELECTRONIC TECHNOLOGIES

Figure 4.36 The different methods used to mount a monolithic die to a substrate Table 4.6 Basic features of the four main monolithic mounting technologies. Adapted from Doane and Franzon (1993)

Relative cost Maximum I/O count Footprint size, die + (mm) Lead inductance (nH) Peripheral bond pitch (mm) Availability of die basic features of these technologies and the following sections explain each method in turn. Harper (1997) provides an excellent overview of this field.

In monolithic mounting, the die is bonded onto the substrate that is part of the IC package. The IC package is then connected up to other electronic circuit components, normally through a printed or hybrid circuit board. IC packages come in a variety of sizes and forms, but the two main types are the dual-in-line13 package (DIP) and surface-mount technology (SMT). DIPs are popular for smaller input-output (I/O) counts, whereas SMT permits higher component densities. Figure 4.37 shows an example of a low-cost plastic DIP, a metal DIP, and a metal SMT package.

Table 4.7 illustrates the characteristics of the common IC packages in terms of their size, electrical characteristics, thermal characteristics, usual gates, and relative cost (Ginsberg 1992).

4.4.1 Die Bonding and Wire Bonding

Die and wire bonding have been used for more than 25 years and involve a two-stage process. First, the die is attached mechanically to the substrate either by an organic adhesive, such as a silver-loaded epoxy, or by a metal solder. This is a low-temperature

13 Sometimes abbreviated to DIL package

MONOLITHIC MOUNTING 101

Figure 4.37 Examples of (a) a plastic DIP; (b) a metal DIP; and (c) a surface-mount package process and care must be taken not to stress the die through differences in the thermal expansions of the materials. Next, the electrical contacts between the die and substrate are made through the bonding of a metal wire (see Figure 4.38). Gold or aluminum wires of varying diameter (or ribbons) can be attached by thermocompression, thermosonic, or ultrasonic bonding. Thermocompression bonding is commonly employed and requires both heat (>300°C) and pressure to join the two metals together, usually by forming a ball or stitch. In ultrasonic wedge bonding, the heat is generated by ultrasound and so the substrate remains around room temperature. Finally, thermosonic bonding uses a combination of ultrasound and pressure, and better results are obtained at intermediate substrate temperatures of 125°C.

4.4.2 Tape-Automated Bonding

Tape-automated bonding (TAB) has a number of advantages over die- and wire-bonding methods. First, TAB connects the die onto the substrate both electrically and mechanically.

The dies are thermocompressively bonded onto tiny beam leads that have been etched in a metal tape (see Figure 4.39).

These inner leads have a smaller pitch than wire bonds and then fan out to a larger pitch that is bonded onto the substrate. The gang bonding of the leads by means of a

Table 4.7 Characteristics of common IC packages. From Ginsberg (1992) pitch 0.75 to 2.3 in body length 0.3 to 0.7 in body width

16 to 28 pins 10 mils pin pitch 50 to 70 mils body length 0.3 to 0.4 in body width 48 to 260 pins 10 mils pin pitch 0.65 to 1.7 in body width

28 to 84 pins 40 to 50 mils pin pitch 0.45 to 0.97 in body width

28 to 84 pins 50 mils pin pitch 0.49 to 1.19 in body width 64 to 299 pins 70 mils pin

pitch 1.033 to 1.7 in body width

Note: R: Resistance, L: Inductance, C: Capacitance. Assumes 1.5 urn CMOS technology for usable gates.

MONOLITHIC MOUNTING 103

Al or Au wire Die or chip

Die-bond material

Figure 4.38 Die- and wire-bonding technique

-TAB lead

— Chip

• Die-bond material Substrate

\

Figure 4.39 Tape-automated bonding technique

hot thermode produces a faster throughput than wire bonding. Moreover, the reduced inductance of a probe means that the devices can be AC-tested.

The disadvantages of TAB include the relatively high cost of the process and the need for a large device footprint. This problem is overcome in flip-chip mounting.

4.4.3 Flip TAB Bonding

In flip TAB bonding, the die is mounted upside down on the substrate, as shown in Figure 4.40. The major advantage of flip TAB over regular TAB mounting is that the die can be subsequently attached to a metal lid for better thermal management.

4.4.4 Flip-Chip Mounting

Finally, flip-chip mounting of the die has a number of key advantages. It provides an excellent contact between the die and substrate by eliminating the wire or beam lead

Chip Flip TAB lead Support material Substrate Figure 4.40 Flip TAB technique

104 STANDARD MICROELECTRONIC TECHNOLOGIES Chip

— Solder bumps

" " - - Substrate Figure 4.41 Flip-chip mounting technique

entirely (see Figure 4.41). Solder bumps are placed on the substrate and then the die is mounted facedown, and the solder is melted to make the connection. The small footprint and pitch, coupled with short interconnect of about 50 urn, and hence low inductance, make this a very attractive technology at a relatively low cost.

Full details of these bonding methods may be found in textbooks such as Doane and Franzon (1993).