Signals Between the 653 Buffer and 654 Controller

Table 3-12 shows the signals that interconnect the 654 Controller with the 653 Buffer.

Table 3-12. Signals Between the 653 Buffer and the 654 Controller

654 Controller 653 654

Signal Name Type Type Description

ADDRHI/DATALO in out Address high/data low. The 654 Controller asserts ADDRHI/DATALO (high) to putthe 653 Buffer in a PCI address cycle and negates ADDRHI/DATALO low to put the 653 Buffer in a PCI data cycle. (The PCLAD[31 :00] bus is a multiplexed address and data bus.)

This signal has two uses-cluring 60X CPU initiated cycles to the PCI bus, the negation transition (signalling .the end of the address tenure) occurs exactly one PCI clock cycle earlier than whenthe data tenure begins. The 653 Buffer delays driving data to the PCLAD bus for one PCI cycle.

During PCI-initiated cycles to system memory, the 653 Buffer latches the PCLAD bus as an address on each PCLCLK rising edge while ADDRHI/DATALO remains asserted high. When ADDRHI/DATALO is negated, the last address remains in the PCI address latch in the 653 Buffer.

The 650 Bridge Chip. Set

Table 3-12. Signals Between the 653 Buffer and the 654 Controller (Continued)

654 Controller 653 654

Signal Name Type Type Description

ALL_ONES_SEL# in out All-ones select, asserted by the 654 Controller to the 653 Buffer to place all one-bits on the 653 Buffer internal data bus. ALL ONES SEL# is used during PCI configuration read transactions to return 64 one~its to the CPU data bus when no PCI device responds and during system memory reads that are out-of-range.

BURST_CLK# in out Burst clock. Based on other control signals, BURST _CLK# clocks the shifts in the ROM shift register, clocks the ROM burst counter, clocks the PCI burst counter during PCI master cycles, or clocks the CPU burst counter (all withi n the 653 Buffer).

CPU_ADDR_OE# in out CPU address output enable. The 654 Controller asserts CPU_ADDR_OE#

to enable the 653 Buffer to assert PCI-initiated addresses on the 60X CPU address bus. The 654 Controller asserts TS# when·the address is valid, allowing the L 1 and L2 caches to snoop memory cycles.

CPU_ADDR_SEL# in out CPU address select. The 654 Controller asserts CPU ADDR SEL# to enable the 653 Buffer to receive addresses from the 60X bus:-The 654 Controller asserts this signal during power-on-reset (POR). After power up, this signal must be asserted and deasserted by the 654 Controller before any bus cycles are initiated. This initializes the CPU burst counter within the 653 Buffer.

CPU_DATA_OE# in out CPU data output enable. The 654 Controller asserts CPU_DATA_OE#

during CPU read cycles to enable the 653 Buffer to assert data onto the 60X bus.

CPU~DATA_SEL# in out CPU data select. The 654 Controller asserts CPU_DATA_SEL#during CPU write cycles to enable the 653 Buffer to receive data (byte-swapped in little-endian mode) from the 60X bus.

ERR_ADDR_SEL# in out Error address select. The 654 Controller asserts ERR ADDR SEL# to enable the 653 Buffer to drive a 32-bit error address from the error address register onto both halves of the 64-bit 60X CPU data bus. MEM_PAR_ERR#

and TT _ERR# are deactivated coincidently with the rising edge of this signal.

L_PCLDATA# in out Latch PCI data. While L PCI DATA# is not asserted and the PCI ClK is low, the PCI data latch is transparent to the PCLAD bus. Whendata is required from the PCI bus (during a CPU to PCI read or a PCI bus master to system memory write), the 654 Controller asserts this signal followi ng the rising edge of the PCLCLK for the current data phase. This latches the current data phase data into the PCI data latch. The 4-byte data is then placed on both halves of the 8-byte653 Buffer internal data bus.

lE_MODE_SEl# in out Little-endian mode select. In response to lE_MODE_REQ#, the 654 Controller asserts LE_MODE_SEL# to set the 653 Buffer to little-endian mode of operation. This signal is switched between bus cycles.

MEM_DATA_OE# in out Memory data output enable. While MEM_DATA_OE# is asserted, the 653 Buffer drives the 64-bit internal data bus and its eight parity signals onto the memory data bus and the memory parity bus. MEM_DATA_ OE# is asserted by the 654 Controller during memory write cycles.

MEM_DATA_SEl# in out Memory data select. MEM_DATA_SEl# is. asserted by the 654 Controller during a memory read transaction. When MEM_DATA_SEL# is asserted, the 653 Buffer uses the memory data bus as the source for the current transaction.

26

The 650 Bridge Chip Set

Table 3-12. Signals Between the 653 Buffer and the 654 Controller (Continued)

654 Controller 653 654

Signal Name Type Type Description

MEM_PAGE_HIT# out in Memory page hit. The 653 Buffer asserts MEM_PAGE_HIT#to indicate an equal compare on the RAS address. This signal is valid one CPU_CLK after the assertion of TS#.

MEM_PAGE_HIT# is not asserted for forced page hits that occur after refresh cycles and PCI 1/0 cycles. The 650 Bridge internally sets a forced page condition for these situations.

MEM_PAR_GOOD out in Memory parity good. Negated by the 653 Buffer to indicate a parity error on a read of system memory. This is an unqualified decode of the 64 memory data lines. The 654 Controller samples this line appropriately.

NO_TRANS in out No translation mode. The 654 Controller asserts NO_TRANS high when a memory read or write cycle runs on the PCI bus on behalf of an ISA master.

NO_TRANS disables the address remapping within the 653 Buffer so that ISA masters that cannot remap the 0 to 16M address range can directly access memory in the 0 to 16M address range.

When NO_TRANS is asserted, all address remapping in the 653 Buffer is disabled.

PC LAD_PAR out in PCI address and data parity. The 653 Buffer generates an even parity bit across the PCLAD[31 :0] lines. This is an unqualified signal that is onlyvalid when the PCI AD bus is valid. The 654 Controller combines PCI AD PAR with PCLC/BE[3:0] to generate PCLPAR, the PCI parity bit. - -PCLOE# in out PCI output enable. While PCLOE# is asserted, the 653 Buffer drives the

internal address or data buses onto the PCI AD bus. PCI OE# is asserted whenever the CPU or L2 is the bus master except during the data phase of reads from the PCI. See the ADDRHI/DATALO signal.

PCLSEL# in out PCI select. The 654 Controller asserts PCLSEL# to enable the 653 Buffer to receive addresses and data from the PCI bus during PCI master cycles to system memory or CPU reads from the PCI. PCLSEL# is asserted for the duration of the cycle.

RASH I/CASLO in out RAS or CAS select. The 654 Controller asserts RASHI/CASLO high for a RAS cycle and negates RASHI/CASLO low for a CAS cycle. This signal is asserted during any PCI 1/0 and configuration cycles, following a DRAM memory page miss, and during DRAM refresh cycles.

REFRESH_SEL# in out DRAM refresh selection. After REFRESH_REQ# is asserted externally, the 654 Controller asserts REFRESH_SEL# as soon as the current CPU or PCI bus cycle concludes in order to initiate a refresh cycle. In response to REFRESH_SEL#, the 653 Buffer places a refresh address on the memory address bus. The 653 Buffer increments its internal row address on the rising edge of this signal.

ROM_SEL# in out ROM select. The 654 Controller asserts ROM_SEL#to signal the 653 Buffer that a ROM cycle is in progress.

N OQ

60XCPU Address Range Oto 2G 2G to 2G + 8M

2G + 8M to 2G + 16M 2G + 16M to 3G - 8M 3G-8M to 3G

3G to 4G-8M

4G-8M to 4G

Table 4-1. 650 Bridge Mapping of 60X CPU Bus Addresses

Other Target Cycle

Conditions Target Cycle Decoded Address Range Comment

System Memory Oto 2G Cacheable by L 1 and L2

CONTIG_IO deasserted PCII/O Cycle o to 64K Non-contiguous 1/0. 32 bytes of each 4K (ISA, EISA, or MicroChannel) (64K to 8M not acces- memory page in this 8M address space are sible) mapped to 32 bytes in the 64K PC 1/0 space.

See Section 4.1.1 and Section 4.1 .2 CONTIG_IO asserted PCII/O Cycle Ot08M Contiguous 1/0. CONTIG_IO is a pin on the

(ISA, EISA, or MicroChannel) 653 Buffer chip. See Section 4.1.1 and 4.1.2 PCI Configuration Cycle 8M to 16M PCLAD[1 :0] forced to OOb

PCII/O Cycle 16M to 1G -8M PCLAD[1 :0] flow through CPU_ADDR[19] = 0 Read Error Address Register None No PCI cycle

CPU_ADDR[19] = 1 PCI Interrupt Acknowledge 1G -8M to 1G PCLAD[1 :0] forced to OOb PCI Memory Cycle o to 1G - 8M PCLAD[1 :0] forced to OOb

Note: CPU space 4G - 16M to 4G - 8M is reserved in PowerPC Reference Platform Specification.

Read cycle ROM Read 1G -8M to 1G System ROM (Can be EPROM, EEPROM,

(0 to 8M in ROM) or flash ROM)

Write cycle ROM Write Port N/A Flash ROM write port (address coded in

(CPU_ADDR[31] = 0) data field)

Write cycle Flash ROM Lock-Out Port N/A Write to this range of addresses locks out

(CPU_ADDR[31] = 1) flash ROM writes until RESET# (No PCI

cycle)

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--Section 4