The IBM27-82650 PCI Bridge chip set (the 650 Bridge) provides an interface that can connect a PowerPC 60X CPU to high-performance PCI (Peripheral Component Interconnect) devices like graphics, LAN, and SCSI controllers. The PCI bus standard defines an environment for high-speed local bus operations. The 650 Bridge chip set provides the necessary control and commu-nications logic to connect a PowerPC 60X CPU to PCI-compliant devices thro.ugh the PCI bus.
The 650 Bridge chip set is comprised of the IBM27-82653 Address and Data Buffer (the 653 Buff-er) and the IBM27-82654 PCI and Memory Controller (the 654 ControllBuff-er). The 650 Bridge sup-ports the PowerPC 601 TM , PowerPC 603 TM , and PowerPC 604 TM microprocessor chips. Within this document, the three microprocessor chips (601,603, and 604) are referred to generically as the 60X CPU. The 650 Bridge supports both the L 1 memory cache of the 60X CPU and an optional L2 cache. Either cache can use write-through or write-back modes of operation.
Local bus standards like PCI and the VL-Bus have evolved to answer the need for higher perfor-mance 1/0 operations on microcomputer systems. The 650 Bridge provides an interface mecha-nism between PowerPC CPUs and the PCI bus. This interface allows system designers to take advantage of the standard PCI controllers that are available for many I/O applications.
The 650 Bridge Chip Set
Figure 1-1 shows a typical PowerPC to PCI system. The address, data, and control signals from the 60X CPU host bus are connected to the 650 Bridge. An optional L2 (level 2) cache can also be connected to the host bus. (The L 1 cache resides in the 60X microprocessor.) The 650 Bridge is connected to the PCllocal bus (address/data and control signals) and also to the DRAM system memory and ROM devices. Communication between the 60X CPU and its I/O devices and sys-tem memory is managed by the 650 Bridge.
1.1 Summary of 650 Bridge Features
This section summarizes the features of the 650 Bridge-including the central arbiter, the memory controller, the PowerPC local bus, the PCI expansion bus, the address translation logic, the L2 cache, the ROM controller, and the interrupt and exception logic.
The 650 Bridge operates from 3.0V to 3.7SV, allowing either 3.3V or 3.6V power sources.
1.1.1 60X Microprocessor Support
The 650 Bridge supports the PowerPC 601,603, and 604 microprocessors as follows:
• PowerPC 601
• Supports all 601 external clocking modes
• Supports CPU bus speedup to 66MHz
• PowerPC 603
• Supports all CPU clock multiplier modes except 1 :1
• Supports CPU bus speed up to 66MHz (Without 1:1 mode, 66MHz:66MHz is not al-lowed, 66MHz:33MHz is alal-lowed, SOMHz:40MHz is allowed.)
• Supports 64-bit mode of the 603 CPU
• PowerPC 604
• Supports all CPU clock multiplier modes
• Supports CPU bus speed up to 66MHz 1.1.2 Central Arbiter
• DRAM refresh support
• Prioritized arbitration among the following devices:
1 . DRAM refresh (highest priority) 2. 60X CPU
3. L2 write-back cache 4. I/O bridge
5. Five PCI masters (priority 5 to 9)
• Support for ISA bus masters when an ISA I/O bridge is installed on the PCI bus
• Operates CPU bus and PCI bus as a single-bus system
• Implements a fairness algorithm
• Has a 63-count PCI bus latency timer to prevent lockup due to inoperative PCI devices
• During idle periods, the PCI bus grant is parked on the 60X CPU 1.1.3 Memory Controller
• Supports memory operations for the PowerPC Architecture TM
• Eight RAS outputs, eight CAS outputs, and two write-enable outputs
• The memory is eight-bytes wide (plus eight parity bits)
• Fast page-mode is supported
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The 650 Bridge Chip Set
• Supports industry-standard 70ns SIMMs
• Directly supports 168-pin eight-byte 8M, 16M, and 32M SIMMs
• Supports 72-pin four-byte 4M, 8M, 16M, and 32M SIMMs
• Mixed use of 8M and 32M eight-byte SIMMs
• Memory configurations available from 8M to 256M
• Empty SIMM sockets are allowed at any position in the eight socket array
• Provides row-address and column-address multiplexing for SIMMs requiring:
10,11, or 12 row by 9 column 10, 11, or 12 row by 10 column 11 row by 11 column
Combined 12 row by 10 column and 11 row by 11 column
• Non-interleaved memory access operation
• Memory refresh address counter
• Auto-increment on every refresh cycle
• Auto-wrap at end of page
• Outputs multiplexed to memory address lines
• Burst-mode memory address generation logic
• 32-byte CPU bursts to and from memory
• Any length PCI burst to and from memory
• Generates even parity, one bit per byte
• Checks parity eight-bytes wide on all memory reads
• Little-endian and big-endian addressing modes
• ISA master to DRAM access
• Optimized Timing is as follows:
• CPU to memory write hit or read hit at 66MHz-7-5-5-5 (CPU bus cycles)
• CPU to memory write hit or read hit at 50MHz, 40MHz, and 33MHz-6-4-4-4
• PCI to memory read hit at 33MHz-5-3-4-3 (PCI bus cycles)
• PCI to memory write hit at 33MHz-5-4-4-4
• See Table 5-10 for more details on memory timing 1.1.4 PowerPC Local Bus
• 64-bit CPU data bus
• 32-bit CPU address bus
• CPU can operate in big-endian or little-end ian mode
• Logic to swap byte lanes and translate addresses for big-endian and little-endian modes
• Synchronous CPU bus speed support up to 66MHz
• PCI bus clock can be equal to or half the speed of CPU bus clock-up to 33MHz 1.1.5 PCI Expansion Bus
• 650 Bridge chip set (653 Buffer and 654 Controller) presents one load to PCI bus
• PCI bus frequency 20 MHz to 33 MHz (maximum of PCI 2.0 specification)
• PCI bus frequency can be equal to or one-half the frequency of the CPU bus clock
• 32-bit multiplexed PCI address and data path
• Support for 1/0 Bus Bridge (lSA, EISA, MicroChannel)
• Support for ISA bus master access to system memory when an 1/0 bridge is in$talled
• PCI to DRAM access-with L 1 and L2 cache snooping
• Supports all 60X to PCI transfers that do not cross a four-byte boundary
The 650 Bridge Chip Set
1.1.6 Address Translation Logic
• Support for memory mapping 60X address space into PCI spaces
• PC I I/O reads and writes
• PCI memory reads and writes
• PCI configuration reads and writes
• PCI interrupt acknowledge reads
• Support for reverse translation of PCI addresses for snoops and PCI to memory access
• Support for contiguous ISA I/O and non-contiguous ISA I/O mappings (non-contiguous I/O allows operating systems to memory-protect 32-byte blocks of ISA I/O space)
• Forces the PCI_AD bits[1 :0] to OOb during the address phase of all PCI transactions ex-cept PCI I/O transactions
• Support for low-order address translation (unmunging) in little-endian mode
• Inputs for translation override 1.1.7 L2 Cache Support
• L2 write-through or write-back cache support
• Handshakes with IBM27-82681-66 PowerPC L2 Cache Controller
• Snoop cycles to CPU generated for PCI reads and writes of system memory
• Parity checking on read cycles
• Allows timing of burst read hits up to 3-1-1-1 1.1.8 System ROM Controller
• Supports up to 8M of 8-bit ROM, flash, or EPROM connected to PCLAD lines
• Conversion buffers support 8-bit to 64-bit conversion
• Logic for flash write
• Write lock-out support
• Single-beat (one-byte to eight-byte) read cycle
• Single-beat (one-byte) write cycle
• Pseudo burst-mode (32-byte) read cycle
• Approximately 1.7us read cycle time at 66MHz 1.1.9 Interrupt and Exception Logic
• Interrupt pass-through to CPU
• Non-maskable interrupt (NMI) support
• The following types of errors are reported:
• CPU or PCI system memory read parity errors
• Illegal transfers:
The CPU attempts an illegal size, type; or alignment transfer A PCI device target aborts to the CPU
A missing or unresponsive PCI device A PCI bus hangup condition
• L2 cache parity errors
• Readable error address register
• Drives CPU data lines to all one-bits on out-of-range memory reads
• PCI configuration cycles return all one-bits when no device responds
• Retimes the soft reset input to meet the 60X specifications
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