The System Error Handler

Table 5-23 summarizes the 654 Controller responses to system errors. The 654 Controller as-serts TT _ERR#, DPE_ERR#, MEM_PAR_ERR#, or ALL_ONES_SEL# in response to an illegal operation or error condition.

The 654 Controller asserts TT _ERR# to report transfer type errors. In response to an error ad-dress read transaction from the 60X CPU (a load word instruction in the range 3G - BM to 3G with CPU_ADDR[19] equal to 0), the 654 asserts ERR_ADDR_SEL# to read out the transfer type error address. TT ~ERR# is asserted by the 654 until the processor performs an error address read transaction.

The 654 Controller asserts MEM_PAR_ERR# to report memory parity errors. In response to an error address read transaction from the 60X CPU, the 654 asserts ERR_ADDR_SEL# to read out the parity error address. MEM_PAR_ERR# is asserted by the 654 until the processor per-forms an error address read transaction.

The 654 Controller does not report an out-of-bounds memory access from the processor as an error. (Memory reads return 64 one-bits.) The 654 stops out-of-bounds PCI to memory cycles with a target abort protocol.

5.8.1 TEA# Error Reporting

The 654 Controller asserts TEA# (transfer error acknowledge) instead of TA# (transfer acknowl-edge) when various conditions are detected. TEA# can be masked by the MASK_ TEA# signal.

When MASK_ TEA# is asserted, TA# overrides TEA# in all circumstances except the Pia cycle error (when XATS# is asserted). MASK_ TEA# can be useful for debugging system errors.

TEA# is asserted to terminate a 60X CPU cycle instead of TA# under the following circumstances:

• On illegal transfer type errors including Pia cycles (XATS# is asserted)

• DPE# data parity errors from the L2 cache-if the error is on the first beat of a burst (INT _CPU# is used for the second, third, and fourth beats. See Section 5.B.2)

• Memory parity errors reported by the 653 Buffer on CPU accesses to system memory

• PCI target aborts

• PCI target timeouts-no response within 60us of PCLDEVSEL# with PCI at 33MHz

• No PCLDEVSEL# from a PCI target within seven PCI clocks from the assertion of PCLFRAME# (except on PCI configuration cycles)

• Illegal transfer sizes and alignments of 60X CPU cycles

• As the response to a PCllnterrupt acknowledge cycle from the 60X CPU following any of the conditions in Section 5.B.2 .

5.8.2 Interrupt Reporting

The 654 Controller asserts the interrupt signal, INT _CPU#, to the 60X CPU to initiate a cycle so . that TEA# can be reported based on the following circumstances:

• When DPE# is asserted by the CPU (two clocks after TA#) on the second, third, or fourth beats of a CPU burst read of an L2 cache.

• Memory parity error on PCI bus mastered cycle. (All subsequent PCI accesses to memory are target aborted.)

• Non-maskable interrupt from the 1/0 bridge.

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INT _CPU# is asserted until the processor initiates a read transaction with the PCI interrupt ac-knowledge address. ALL_ONES_SEL# is driven during the interrupt acac-knowledge cycle, which causes all one-bits to be read as the address, along with TEA# (if MASK_ TEA# is deasserted).

Table 5-23. System Error Reporting

654 Controller Error Status

Activity Description Response Signals Asserted

601-lnitiated Memory Out-of-Range Read TA#, ALL_ONES_SEL# none Transactions

Memory Out-of-Range Write TA# (no write occurs) none 2-Byte transfer with A29-31 = 111 TEA# TT_ERR#

3-Byte transfer with A29-31 = 11 0, 111 4-Byte transfer with

A29-31 = 101,110,111 5,6, or 7-Byte transfer

8-Byte transfer with A29-31 not = 000

Parity Error from 653 Buffer TEA# MEM_PAR_ERR#

Processor/L2 DPE# TEA# (or INT _CPU#) DPE_ERR# (pulsed)

PIO Cycle: XATS# asserted TEA# TT_ERR#

ecowx TA# none

eciwx TA#, ALL_ONES_SEL# none

601 to PCI Master Abort (except Config.) TEA#, TT_ERR#

ALL_ONES_SEL# (read)

Configuration RIW Master Abort TA#, none

ALL_ONES_SEL# (read)

Target Abort TEA# TT_ERR#

Target Retry ARTRY# none

PCI to Memory Master Abort none none

Memory out-of-bounds Target abort, INT_CPU# TT_ERR#

Parity Error Drive PCLPAR invalid on MEM_PAR_ERR#

current cycle. Target abort all following cycles until a read of the error address register, INT _CPU#.

NMI Non-maskable interrupt INT_CPU# none

Interrupt Due to above error conditions and NMI TEA# no change Acknowledge

Cycle

Read Error Due to above error conditions TA#,ERR_ADDR_SEL# Deassert TT ERR# and

Address Latch MEM_PAR_ERR#

The 650 Bridge Chip Set

5.8.3 Saving Memory Parity Error Addresses

Memory parity generation and checking is supported within the 653 Buffer and controlled by the 654 Controller in conjunction with transfer type errors as shown in Figure 5-22. The 653 Buffer has an internal register that stores the address on memory parity errors. Each processor or PCI to memory access latches the address onto the error address register within the 653 Buffer as long as the signal L_ERR_ADDR# is asserted. On a memory access with a parity error from the 653 Bridge (MEM_PAR_GOOD deasserted), MEM_PAR_ERR# is asserted low to inhibit latching new addresses into the 653 Buffer error address register by means of the support gate shown in Figure 5-22.

Figure 5-22. Error Address External Support Gate

MEM_PAR_ERR# remains asserted until the end of the cycle that the 60X CPU accesses the contents of the 653 Buffer error address register. The 654 Controller asserts ERR_ADDR_SEL#

to the 653 Buffer when the 60X CPU reads the error address register. The stored error address is then read back to the CPU.

The 653 Buffer asserts the error address register on both words of the double-word 60X CPU data bus so that reads of either word get the error address. At the end of the error address read cycle, MEM_PAR_ERR#, TT _ERR# and ERR_ADDR_SEL# are all deasserted.

The 654 Controller does not report an out-of-bounds memory access from the processor, but it does stop an out-of-bounds PCI to system memory cycle with the target abort protocol.

5.8.4 Oata·Parity Error (OPE_ERR#)

The 654 Controller asserts DPE_ERR# in response to a data parity error (DPE#) from an L2 cache access. DPE_ERR# is asserted for two 60X CPU bus clocks for each data parity error detected.

5.8.5 Transfer Type Error

The 654 Controller asserts TT _ERR# to report transfer type errors. TT _ERR# is asserted until the 60X CPU accesses the error address register within the 653 Buffer.

Transfer type error (TT _ERR#) cycles include:

• PIO cycles-XATS# asserted (not masked by MASK_TEA#)

• A 60X CPU transfer size of five, six, or seven bytes to system memory or PCI

• A 60X CPU transfer size of two, three, or four bytes crossing a word boundary when target is PCI or system memory

• A 60X CPU transfer size of five to eight bytes when target is PCI

• A 60X CPU burst when the target is PCI

• A PCI target abort

• No PCLDEVSEL# from target-except on PCI configuration cycles

• A PCI target system time-out-if no response 60us (33MHz PCI) after PCLDEVSEL#

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The 654 Controller does not report an out-of-bounds memory access from a PCI master to system memory, but it does stop an out-of-bounds PCI cycle to system memory with target abort protocol.

On detection of a transfer-type error, the 654 Controller asserts TT _ERR# to inhibit latching new addresses into the 653 Buffer error address register (see Figure 5-22). TT _ERR# remains as-serted until the end of the cycle when the 60X CPU reads the error address register.

The 654 Controller asserts ERR_ADDR_SEL# to the 053 Buffer when the 60X CPU reads the error address register. The 653 Buffer asserts the error address register on both words of tt)e 60X CPU data bus. At the end of the error address read cycle, TT _ERR# and ERR_ADDR_SEL# are deasserted.

5.8.6 Illegal pel Operations

If the PCI bus runs a cycle to an out-of-bounds system memory address, the 654 Controller uses the target abort protocol to stop the PCI cycle.

5.8.7 Non-Maskable Interrupt (NMI_REQ)

The 654 Controller asserts INT _CPU# in response to NMLREQ. When the 60X CPU drives a PCI interrupt acknowledge transaction back in response to INT _CPU#, the 654 Controller im-mediately asserts TEA# and 64 one-bits on the CPU data bus without generating a PCI interrupt acknowledge transaction. An interrupt acknowledge cycle that is immediately terminated by TEA# is the result of one of the conditions listed in Section 5.8.2.

The 650 Bridge Chip Set

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Section 6