650 Bridge Pin Descriptions

Figure 3-1 shows how the 653 Buffer and 654 Controller are connected to the 60X CPU bus, the PCI bus, DRAM, ROM, the L2 cache, and external logic. Figure 3-1 also shows the interconnec-tions between the 653 Buffer and the 654 Controller. The following tables describe groups of sig-nals that connect to the 653 Buffer and 654 Controller.

The tables in Section 3.2 describe the pins that connect the 653 Buffer with the 60X CPU, the PCI bus, system memory (DRAM), and external logic. The tables in Section 3.2 describe the pins in the 654 Controller. The tables in Section 3.3 describe the pins that interconnect the 653 Buffer and the 654 Controller.

Section 8.1 and Section 8.2 contain numeric and alphabetic lists of the pins in the 653 Buffer and 654 Controller respectively. Pin numbers are included in these tables.

3.1 653 Buffer Pin Descriptions

The # symbol at the end of a signal name indicates that the active or asserted state of the signal occurs with a low voltage level. When the # symbol is not present after the signal name, the signal is asserted with a high voltage level.

The terms asserted and negated are used extensively. The term asserted indicates that a signal is active, regardless of whether that level is represented by a high or low voltage. The term ne-gated means that a signal is inactive. The term deasserted is also used to indicate

a

The following terms are used to describe the signal type:

in Input is a standard input-only signal.

out Output is a standard active driver I/O Bi-directional

The 650 Bridge Chip Set

Figure 3-1. 650 Bridge Pin Connections

16

The 650 Bridge Chip Set

3.1.1 653 Buffer to 60X CPU Bus Interface Signals

Table 3-1 describes the signals that interface the 653 Buffer to the 60X CPU bus.

Table 3-1. 653 Buffer to 60X CPU Bus Interface Signal Name Type Description

CPU_ADDR[0:31 ] 1/0 The 60X CPU address bus, bit a = most-significant bit (MSB). All buses connected to the 650 Bridge, except the 60X buses, use little-endian nomenclature.

CPU_DATA[0:63] 1/0 The 64-bit 60X CPU data bus, bit 0= MSB. CPU_DATA[0:31] connect to the 60X CPU signals DH[0:31]. CPU_DATA[32:63] connect to the 60X CPU signals Dl[0:31].

TSIZ[0:2] in 60X CPU bus transfer size-number of bytes. The 650 Bridge supports transfers of 1, 2, 3, 4, 8, and 32 bytes (1, 2, 3, or 4 to the PCI bus).

3.1.2 653 Buffer to PCI Bus Interface Signals

Table 3-2 describes the signals that interface the 653 Buffer to the PCI bus.

Table 3-2. 653 Buffer to PCI Bus Interface Signal Name Type Description

PCLAD[31 :0] 1/0 PCI address and data bus. The 32-bit PCLAD bus is a multiplexed address and data bus.

The PCLAD bus is numbered in little-end ian order.

PCLClK in PCI clock. The PCI clock signal-up to 33MHz. The rising edge of the PCI_ClK signal at the 653 Buffer must be synchronized to the rising edge of CPU_ClK within -1.0ns to + 1.0ns. The PCLClKcan bethe same frequency or halfthefrequency of the CPU clock.

The PCI clock at the 653 Buffer mayor may not be the same physical signal line as the PCI clock at the 654 Controller. See Section 7.2 for clocking details.

3.1.3 653 Buffer to System Memory Interface Signals

Table 3-3 describes the signals that interface the 653 Buffer to system memory.

Table 3-3. 653 Buffer to System Memory Interface Signal Name Type Description

MEM_ADDR[11 :0] out Memory address bus. MEM_ADDR is 12 bits, multiplexed, and little-endian. While the 654 Controller asserts RASHI/CASlO high, the MEM_ADDR lines contain row addresses selected from the internal address bus of the 653 Buffer. While RASHI/CASlO is low, the MEM_ADDR lines contain the column addresses.

MEM_ADDRO_B out A duplicate of MEM_ADDR[O]. (Required by some SIMMs.) MEM_DATA[63:0] 1/0 64-bit memory data bus. MEM_DATA[63] is the most significant bit.

MEM_PAR[7:0] I/O 8-bit memory parity bus. MEM_PAR[7] is the most significant bit. Bit 7 corresponds to MEM_DATA[63:56]. Even parity is generated and written on memory write cycles.

System memory is always read in eight-byte double words, regardless of the transfer size requested. Parity across eight bytes is checked on all memory read cycles.

The 650 Bridge Chip Set

3.1.4 653 Buffer to External Logic and System Interface Signals

Table 3-4 describes the signals that are used to interface the 653 Buffer to the rest of the system via external logic, command bit storage elements, the test interface, power, and ground.

Table 3-4. 653 Buffer to External Logic and System Interface Signal Name Type Description

CONTIG_IO in Contiguous 1/0. External logic asserts CONTIG_IO high to enable direct mapping of addresses from 2G to 2G + 8M. When CONTIG_IO is driven low, it enables non-contiguous addressing in the 2G to 2G + 8M address range. Non-contiguous 1/0 is a mapping of the low 32 bytes of each 4k page of CPU memory space to 32 bytes of PCI/ISA 1/0 space. See Section 4.1.1 and 4.1.2.

This signal should only be changed between 60X to PCII/O cycles.

DRAMX9HI/X10LO in DRAM type. DRAMX9HI/X1 OLO is asserted high for addressing DRAMs with nine column address bits (X9 mode), low for X1

a

L_ERR_ADDR# in Latch error address. The address on the 653 Buffer internal address bus is latched into the 653 error address register while L_ERR_ADDR# is asserted. This signal can be derived by external logic from the 654 Controller signals TT _ERR#, MEM_PAR_ERR# and, optionally, any other signal indicating an error condition requiring the address to be latched. L_ERR_ADDR# must be held asserted to hold the contents of the latch. Any signal used with TT _ERR# and MEM_PAR_ERR# to derive L_ERR_ADDR# must also be held until after the latch is read.

This diagram illustrates support logic needed to latch the address of memory parity errors or transfer type errors.

TT_ERR#

~

MEM_PAR_ERR# Gate

from 654 to 653

TEST# in Test mode. Pull to logic high during normal operation. Assert TEST#, L_ERR_ADDR#, and ERR_ADDR_SEL# to tri-state the outputs.