The PCI Local Bus Review

This section provides a review of the operation of the PCllocal bus. The PCllocal bus standard defines a high-performance, 32-bit or 64-bit local bus with multiplexed address and data lines. The PCI local bus standard has been defined by the PCI SIG (Special Interest Group), a computer-industry standards group. The PCI local bus provides an interconnect mechanism between pe-ripheral controllers, like graphics controllers and SCSI controllers, and host computer systems.

2.1.1 PCI Local Bus References

The PCI Local Bus Specification, Production Version, Revision 2.0, dated April 30, 1993 contains the detailed information necessary for a full understanding of the PCI bus standard. The 650 Bridge provides the signals that are necessary to interact with devices that conform with the PCI standard as described in the specification. Implementing a PowerPC to PCI system with the 650 Bridge requires a full understanding of the PCI standard.

2.1.2 PCI Local Bus Overview

The PCI bus can be either a 32-bit or a 64-bit multiplexed address/data bus implementation. The 650 Bridge is a 32-bit implementation. The 32-bit multiplexed address and data lines can encode addresses in the range of 0 to 4G (0000 OOOOh to FFFF FFFFh). During data phases, the 32-bit bus can transfer four bytes per phase. A PCI bus transaction consists of an address phase fol-lowed by one or more data phases.

The PCI bus can operate in single-beat or burst mode. The beginning address of a transfer can be followed by a variable number of consecutive 32-bit data words. Burst data transfer can occur at the rate of 32 bits per PCI bus clock cycle. The maximum PCI clock rate of 33MHz can support up to 132M bytes per second burst transfer rates.

The 650 Bridge Chip Set

2.1.3 PCI Signals

Table 2-1 shows the standard PCI signals that are interfaced directly with the 650 Bridge chip set.

The column labeled PCI Signal Name contains the signal name that is used in the PCI standard document. The column labeled 650 Bridge Signal Name contains the 650 Bridge signal name for the PCI signal. The PCI Local Bus Specification document describes all the possible PCI signals.

The # symbol at the end of a signal name indicates that the active or asserted state of the signal occurs with a low voltage level. When the # symbol is not present after the signal name, the signal is asserted with a high voltage level.

The terms assert and negate are used extensively. The term assert indicates that a signal is ac-tive, regardless of whether that level is represented by a high or low voltage. The term negate means that a signal is inactive. The term deasserted is also used to indicate a signal that is ne-gated.

Table 2-1. PCI Signals in the 650 Bridge

PCI 650 Bridge

Family Signal Name Signal Name Description

Address/Data AD[31 :00] PCLAD[31 :00] Address and data bus, 32 bits multiplexed.

C/BE[3:0]# PCL C/BE[3 :0]# C (bus command) and BE (byte enable) multiplexed lines.

An address phase is a bus command, a data phase is BE.

PAR PCLPAR Parity bit for PCLAD and PCLC/BE# combined, even par-ity bit for the combination of 36 bits.

Arbitration REQ# IO_BRDG_REQ# ISA or EISA PCI bus request, input to arbiter.

GNT# IO_BRDG_GNT# ISA or EISA PCI bus grant, output from arbiter.

REQ# PCLREQ[1 :5]# Five PCI bus request lines, input to arbiter.

GNT# PCLGNT[1 :5]# Five PCI bus grant lines, output from arbiter.

Interface Control FRAME# PCLFRAME# PCI frame, asserted by the current master to indicate the beginning and duration of a bus access.

TRDY# PCLTRDY# PCI target ready, asserted by the target device to indicate

·its completion of the current data phase of a transaction.

IRDY# PCURDY# PCI initiator ready, asserted by the master device to indi-cate completion of the current data phase of a transaction.

When PCI TRDY# and PCI IRDY# are asserted on the same bus clock cycle, the current data phase is complete.

STOP# PC LSTOP# PCI stop, asserted by a target to stop a transaction.

DEVSEl# PCLDEVSEl# PCI device select, asserted by a device that claims the address range and bus command of a cycle on the PCI bus.

System ClK PCLClK PCI clock, provides the timing for PCI transactions (up to 33MHz).

RST# RESET# Reset, initializes PCI registers, signals, and sequencers.

6

The 650 Bridge Chip Set

2.1.4 PCI Masters and Targets

The PCI bus standard uses a master and target architecture. Master devices can gain control of the bus and then direct other devices to perform reads, writes, configuration operations, and other types of transactions. Masters on the PCI bus use dedicated REQ# and GNT# lines to gain control of the bus. Targets on the PCI bus do not use REQ# and GNT# lines. Targets are selected by a range of addresses within the various types of PCI transactions.

A PCI master device requests the bus by asserting its REQ# line. When the GNT# line for the requesting master device is asserted, the master device can then take control of the PCI bus to communicate with other master or target devices on the PCI bus. An arbiter (which the 650 Bridge provides) is necessary to manage the REQ# and GNT# activity on the PCI bus.

2.1.5 PCI Arbitration

Since there can be more than one PCI master device on the PCI bus, and since each master de-vice has its own independent REQ# and GNT# lines, there must be an arbitration mechanism for any PCI bus implementation. The 650 Bridge incorporates arbitration logic for ,DRAM refresh cycles, the 60X CPU, the L2 cache, an liD bridge (ISA, EISA, MicroChannel), and up to five other PCI master devices. The 650 Bridge arbitration logic ensures PCllatency requirements and allo-cates host and PCI bus accesses according to a priority and fairness algorithm.

2.1.6 Basic Transfer Control

After PCLREQ# and PCLGNT#, the fundamentals of all PCI data transfers are controlled with the following five signals:

1. PCLFRAME#-which is asserted by the master to indicate the beginning and end of a PCI bus transaction.

2. PCLDEVSEL#-PCI device select, when asserted, indicates that the device that is driving PCLDEVSEL# has decoded its address as the target of the current address.

3. PCLIRDY#-initiator ready, deasserted by the master to force wait states.

4. PCL TRDY#-target ready, deasserted by the target to force wait states.

5. PCLSTOP#-PCI stop is asserted by a target to stop a transaction.

The PCI bus is idle when both PCLFRAME# and PCLIRDY# are deasserted. The first clock edge on which PCLFRAME# is asserted is the address phase. The 32-bit address and 4-bit bus com-mand code (PCLC/BE[3:0]#) are asserted (see Section 2.1.7) on the PCI bus during the address phase.

Target devices have up to three PCI bus cycles after PCLFRAME# is asserted to recognize an address and respond by asserting PCLDEVSEL#. If no device asserts PCLDEVSEL# within three clocks of PCLFRAME# a device using subtractive decode can claim the transaction byas-serting PCLDEVSEL#. A PCI device that provides ISA, EISA, or MicroChannel bus logic usually uses subtractive decoding for device selection.

One or more data phases follow the address phase. The master is required to assert its IRDY#

signal when it is ready to receive or when it is providing valid data. The target asserts its TRDY signal when it is ready to receive or when it is providing valid data. When PCLTRDY# and PCLIRDY# occur on the same bus cycle, the current data phase is concluded.

When the last data phase begins, the master deasserts PCLFRAME# to indicate the last 32-bit transfer. For single-cycle transfers, PCLFRAME# is deasserted on the first data phase.

The 650 Bridge Chip Set

2.1.7 PCI Bus Commands

During the address phase of a PCI transaction, the PCLC/BE[3:0]# signals encode bus com-mands. (During the data phase on the PCI bus, the PCLC/BE[3:0]# signals are byte enables for the four bytes on the PCLAD[31 :00] address/data bus.) Table 2-2 shows the 16 possible PCI bus commands. During the address phase on the PCI bus these bus commands determine the action that is to be taken by the target of the address phase.

Table 2-2. PCI Bus Commands PCI_C/BE[3:0]# Command Type

OOOOb Interrupt Acknowledge 000lb Special Cycle

0010b I/O Read

00llb I/O Write

0100b Reserved

0101b Reserved

0110b Memory Read

0111b Memory Write

. 1000b Reserved

1001b Reserved

1010b Configuration Read 1011b Configuration Write 1100b Memory Read Multiple 1101b Dual Address Cycle 1110b Memory Read Line

l111b Memory Write and Invalidate 2.1.8 Termination of PCI Cycles

PCI transactions can be terminated in the following non-standard ways:

• Master abort-The master deasserts FRAME# then deasserts IRDY#

• Target abort-The target asserts PCLSTOP# with PCLDEVSEL# deasserted

• Target retry or disconnect-The target asserts both PCLSTOP# and PCI_DEVSEL#