Figure 4-12 shows a 60X CPU to PCI write with XADIO
=
0, during which TS# is asserted across the falling edge of PCLClK rather than across the rising edge of PCLClK. Most of the timing diagrams show TS# asserted across a rising edge of PCLClK, but it is equally likely that TS#will be asserted across a falling edge of PCLClK. When this happens, the 650 Bridge responds by stretching the transaction, effectively adding a CPU_ClK wait cycle after CPU_ClK 3 to syn-chronize the transaction to PCLClK. The rest of the transaction remains unchanged.
Figure 4-13 shows a 60X CPU to PCI write with XADIO = 1 , during which the target device asserts a target retry (PCLSTOP# and PCLDEVSEl# asserted together). A PCI device can target retry a transaction for various reasons. Following a target retry, the initiating device can retry the trans-action.
46
"11
"T1
o 2 3 4 5 6 7 8 9 10, 11 , 12 , 13 , 14 , 15 , 16 , 17
The 650 Bridge Chip Set
4.3.12 pel to Memory Read-Single-Beat, Page Hit
During PCI to memory transactions, the 650 Bridge updates the PCI address latch in the 653 Buff-eron each rising edge of the PCLClKwhileADDRHl/DATAlO is high, so in Figure 4-15, the PCI address latch is updated on PCLClK 1. Also on PCLClK 1, the 650 Bridge samples PCLFRAME# active, which starts the 650 Bridge PCI target cycle (assuming that the PCI bus master is addressing system memory).
The 654 Controller sends ADDRHI/DATAlO low on PCLClK 1 to hold the PCI address in the latch. PCLTRDY#, PCLDEVSEl#, and PCLSTOP# have been tri-stated since the beginning of the cycle; on PCLClK 2, the 650 asserts PCLDEVSEl# to claim the transaction, and drives PCLSTOP# and PCLTRDY# high. The 654 Controller asserts PCLOE# on PCLClK 2 to en-able the PCLAD drivers in the 653 Buffer (the cycle between PCLClKs 1 and 2 is a turn-around cycle (TAC) for the PCLAD lines, and some control lines). '
The 654 Controller begins a CAS# read to the memory. This CAS# read is similar to that used when the CPU is reading system memory. The 653 Buffer drives valid data onto the PCLAD lines in time to meet the required PCI data setup times for PCLClK 5, so the 654 Controller asserts PCL TRDY# on PCL ClK 4. The 654 Controller then negates PCL TRDY#, PCLDEVSEl#, and PC LSTOP#, and negates PCLOE# to tri-state the PCLAD lines. The 654 Controller tri-states PCLTRDY#, PCLDEVSEl#, and PCLSTOP# on PCLClK 6 (see notes 1 and 2).
The 650 Bridge generates a snoop cycle on the 60X CPU bus for each PCI to system memory transaction. In this transaction (Figure 4-15), CPU_ADDR_OE# has been asserted (see note 1), so the 653 Buffer is driving the (translated) PCI address onto the CPU address lines. The 654 Controller asserts TS# for one CPU_ClK cycle, followed by asserting AACK# for one CPU_ClK cycle, in compliance with 60X CPU bus snoop cycle requirements. Should either the l1 or l2 caches detect a cache hit, it must assert ARTRY# so that it is sampled valid at least by the second CPU_ClK after it samples TS# valid, or it is not recognized.
These notes refer to Figure 4-15 and to following figures as appropriate.
1. During PCI to memory transactions, the 654 Controller drives PCLSEl#,
CPU_ADDR_OE#, and AACK# depending on two factors-the state of the transac-tion engine and the state of the arbiter engine. Depending on the status of the system on the rising edge of the PCLClK on which the 654 tri-states PCLTRDY# (in this case PCLClK 6), the arbiter either removes the grant from the current PCI bus mas-ter or that bus masmas-ter retains masmas-tership of the system. If the PCI bus masmas-ter retains the grant, the 654 leaves PCLSEl# and CPU_ADDR_OE# low, and continues to drive AACK# high into the next cycle. If the PCI bus master is losing the grant, then (on the rising edge of the PCLClK on which the 654 tri-states PCLTRDY#) the 654 drives PCLSEl# and CPU_ADDR_OE# high, and tri-statesAACK#. See Table 4-3.
Table 4-3. Effects of Arbiter on Three Signals
Signal pel Retains System Mastership pel Loses System Mastership
PCLSEl# Remains driven low. Is driven high.
CPU_ADDR_OE# Remains driven low. Is driven high.
. AACK# Remains driven high. Is tri-stated .
50
The 650 Bridge Chip Set 2. During PCI to memory read transactions, ADDRHI/DATALO is deasserted on the
PCLCLK that the 654 Controller tri-states PCLTRDY# (in this case PCLCLK 6). Dur-ing PCI to memory writes, the 654 deasserts ADDRHI/DATALO one PCLCLK earlier.
3. ISA master devices can access system memory from 0 to 16M with a direct address of 0 to 16M. See Section 5.6.1.2 and Section 5.6.1.3.
2 3 4 5 6
PCCCLK.
7 CIBE[3:0]#
:::x...".=-:--J'--________ -:--_ _ _ _ _ --:---', _ _ _ _ _ _
TAC'
PC CAD [PCI]
---<[]AWd:wdrc:::::J----1£~----;----_;_~----;---;----\ I
\ I
, I
CAS# , \ ' , I '
MEM_DATA --,-~--,-~--_,--~--,-~tl~,Ss:::~::::::~,:(:}--
PCCOE# \ ' I I I
PCCAD --~-~--~--~--~f~7~7~7ZZ727~7~7~~H~~S~SIj==':::J--~---CPU_ADDR_OE# _____ ~ __ ---~--~----~---~----~~/~(I~,)-.--, ' ,
CPU_ADDR __ ~_X,~
__
--~$=n=oo~p~A=d=dr~y=ss~--~---~---~---~TS#
AACK#
ARTRY#
BILE_PAR_EN#
I~I
Snoop,
, \ (1,)
\ (I')
\~~, --~-~~-~--~--~,~I
,
Figure 4-15. PCI to Memory Read, Single-Beat, Page Hit Timing DiagramThe 650 Bridge Chip Set
4.3.13 PCI to Memory Read-Burst, Page Hit Then Miss
When
a
PCI bus master is reading from system memory in burst-mode, a page miss can occur at any point in the transaction. Figure 4-17 shows this type of page hit and page miss activity.During PCI to memory reads, each data phase requests up to four bytes from the 650 bridge, but the 650 Bridge always reads eight bytes from the memory subsystem (see Figure 4-16). During burst reads that start on an eight-byte boundary (PC'-AD[2] = 0 during the address phase), the 650 Bridge performs the following steps:
1. Reads eight bytes from memory (and generates a snoop cycle to the 60X bus), 2. Delivers the lower four bytes to the PCI for the first data phase,
3. Delivers the upper four bytes to the PCI for the second data phase, 4. Reads another eight bytes from memory (and generates a snoop cycle), 5. Delivers the lower four bytes to the PCI for the third data phase,
6. Delivers the upper four bytes to the PCI for the fourth data phase, 7. Repeats steps 4., 5., and 6. as required.
With a 2:1 CPU bus to PCI bus clocking mode, this process yields burst read performance (as-suming no page misses) of 5-4-3-4-3-4-3-, etc.
During burst reads that start on a four-byte but not an eight-byte boundary (PC'-AD[2] = 1 during the address phase), the 650 Bridge performs the following steps:
1. Reads eight bytes from memory (and generates a snoop cycle to the 60X bus), 2. Delivers the upper four bytes to the PCI for the first data phase,
3. Reads another eight bytes from memory (and generates a snoop cycle), 4. Delivers the lower four bytes to the PCI for the second data phase, 5. Delivers the upper four bytes to the PCI for the third data phase, 6. Repeats steps 3., 4., and 5. as required.
With a 2:1 CPU bus to PCI bus clocking mode, this process yields burst read performance (as-suming no page misses) of 5-4-4-3-4-3-4-3-, etc ..
PC,-AD 2 =1 Address Phase : 7654
: 715 41
3 2 1
o!:: ~~~Ory
To PCI 1 st Data Phas
7654 From
Memory
To PCI To PCI 2nd Data Phas
From Memory
To PCI To PCI 3rd Data Phas
17 654 3
1
1O~~~~Ory
To PCI 13 2 1 0 To PCI 4th Data Phas Figure 4-16. PCI To Memory Burst Read Transaction
52
."
The 650 Bridge Chip Set
4.3.14 PCI to Memory Write-Burst, Page Miss Then Hit
During PCI to memory writes, the 650 Bridge asserts WE# on PCL ClK 2 to begin the DRAM write operation, and asserts MEM_DATA_OE# on PCLClK 2 to enable the 653 Buffer to drive data onto the MEM_DATA bus.
In Figure 4-18, the 653 Buffer negates MEM_PAGE_HIT# on PCLClK 2 to signal a page miss to the 654 Controller, which then begins a RAS# access. This RAS# access is similar to the one that the 654 Controller executes during a 60X CPU to memory page miss. After the RAS# access completes, the 654 Controller executes CAS# writes, which are also similar to those executed by the 654 during 60X CPU to memory writes.
t '
Figure 4-18. PCI to Memory Write, Burst, Page Miss Then Hit Timing Diagram
54