Electrical Characteristics - PowerPC to PCI Bridge

Unless otherwise noted, all specifications in this section apply to both the 653 Buffer and to the 654 Controller.

6.1 Absolute Maximum Ratings

Stresses in excess of those listed in Table 6-1 may damage and/or decrease the reliability of the 650 Bridge. Additionally, stressing the 650 Bridge in excess of the conditions listed as Recom-mended Operating Conditions is neither intended nor supported. All voltages are referenced to ground (Vss).

Table 6-1. Absolute Maximum Ratings, 650 Bridge

Symbol Parameter Min Max Units

Tjst Junction Temperature, Storage -40 125 deg C

Tjp Junction Temperature, Power Applied -25 100 deg C

VDD Supply Voltage 2.7 3.9 V

Vi DC Voltage Applied to Any Input -.5 5.5 V

Vo DC Voltage Applied to Any Output (Output Tri-stated) . -.5 5.5 V

ESD Withstand 2.2 - kV

Latchup current 100

-

The 650 Bridge Chip Set

6.2 Recommended Operating Conditions

This section lists the conditions under which the 650 Bridge is intended to operate.

6.2.1 Signal And Temperature Ranges

Table 6-2. Recommended Operating Conditions, 650 Bridge

Symbol Parameter Min Max Units Notes

Voo Supply Voltage 3.0 3.8 v

VI DC Voltage Applied to Any Input Pin -.5 5.5 v (1 ) Vo DC Voltage Applied to Any Output Pin -.5 5.5 v (2) Top Junction Temperature, Operating 10 85 deg C

Notes For Table 6-2:

1) Allowed range of DC voltage applied to any 1/0 pin in input mode or to any input pin. The pins shown as Type = PCI may conduct excess current if forced above Voo + 1.Sv.

2) Allowed range of DC voltage applied to any output pin while the output is tri-stated. The pins shown as Type = PCI may conduct excess current if forced above Voo + 1.5v.

6.2.2 Power Dissipation

Neither the 653 Buffer nor the 654 Controller are expected to require a heat sink, when used in the manner described in this manual. However, thermal management is'a complex discipline, and the application is the responsibility of the designer.

Table 6-3 lists the power supply current and power dissipation under various conditions for the 653 Buffer and the 654 Controller.

Table 6-3. Power Dissipation (See Note 1)

Parameter Current Power Notes

(mA) (mW)

Typ Max Typ Max Notes Power Supply Current - System quiescent. 653 43.7 - 157 - (2)

654 8.0 - 29 - (2)

Power Supply Current - Memory accesses with 653 48.0

-

173 - (3) PCI bus idle.

654 19 - 68 - (3)

Power Supply Current - Worst case activity. 653 59 118 212 425 (4) 654 63 126 227 454 (4) Notes for Table 6-3:

1) 60X CPU bus running at 66MHz, PCI bus running at 33MHz and 3.3v, L2 Cache installed, 5 PClloads, 8 DRAM loads, 653 Buffer and 654 Controller at Voo

=

3.6v. This data assumes that the 650 Bridge is connected in a manner similar to that shoyvn in the example system.

2) 60X CPU executing from L 1 cache, DRAM refresh enabled, PCI bus idle.

3) 60X CPU executing repeated burst memory transfers.

112

The 650 Bridge Chip Set

4) A mix of instruction fetches and PCI accesses with addresses broadcast to the CPU bus for snooping

5) The 653 Buffer is supplied in a 304 pin Ceramic (C4) Quad Flat Pack 6) The 654 Controller is suppli.ed in a 160 pin Plastic Quad Flat Pack 6.2.3 Thermal Characteristics

Table 6-4 shows typical thermal resistances associated with the 653 Buffer and the 654 Control-ler. Each row shows data for a given air flow condition at the chip package. The row titled Convec-tion shows data for the chip package in free air with no forced air cooling, with the package mounted horizontally on the upper surface of a PCB. The other rows show data for a variety of forced air flow conditions. The values shown do not include a significant amount of heat flow through the pins of the chip, either to or from the PCB.

From Table 6-3, the worst case power dissipation of either the 653 Buffer or the 654 Controller is less than .5 W. Using TJ(max)

=

85 deg C, and TA

=

50 deg C;

85 C -50 C

8j-a (max) = - - - - - - - = 70 deg C/W

Pd .5W

Examination of Table 6-4 shows that neither the 653 Buffer or the 654 Controller require a heat sink, even with worst case power dissipation, to maintain a junction temperature of less than 85 deg C in free air at 50 deg C ambient. .

Table 6-4. Typical Thermal Resistance, Junction to Ambient, No Heat Sink Airflow Hj-a, 653 Buffer 8j-a, 654 Controller Units

Convection 33.4 54 deg C/W

.25 Mis (50fpm) 29.7 47 deg C/W

.5 Mis (1 OOfpm) 26.8 44 deg C/W

1 Mis (200fpm) 24.0 40 deg C/W

The 650' Bridge Chip Set

6.3 Common Characteristics

The specifications shown in Table 6-5 are common to both the 653 Buffer and the 654 Controller.

Table 6-5. 650 Bridge Common Characteristics (See Note 1)

Symbol Parameter Type Min Max Units Notes

VIL I nput Low Voltage All

-

.8 v (2)

VIH Input High Voltage All 2.0

-

v (2)

IlL Input Leakage Current All - 1 uA (2)

VOL Output Low Voltage TTL

-

.40 v (3)

PCI

-

.55 v (3)

VOH Output High Voltage TTL 2.4

-

v (3)

PCI 2.4

-

v (3)

1038 Output Tri-state Leakage Current TTL

-

10 uA (3)

PCI

-

70 uA (3)

Notes for Table 6-5:

1) Over Recommended Operating Conditions.

2) Values apply to each liD pin in input mode and to each input pin.

3) Values apply to each output pin and to each liD pin in output mode.

6.4 Package/Pin Electrical Characteristics

6.4.1 653 Buffer Model

The electrical model of the effects of package and pin parasitic effects on the 653 Buffer is shown in Figure 6-1. The ranges of values shown are nominal only, are not guaranteed, and vary from pin to pin. The lower values are typical of pins that are located on the side of the package and which are closest to the chip. The higher values are typical of corner pins. Note that the C 1 capaci-tance is the value shown for DPC (Die Pad Capacicapaci-tance) in Table 6-6 (which is due to the liD book). C2 represents a distributed capacitance, and L 1 represents a lumped loop inductance which includes the effects of inductance from the driver book to the power supply pins.

Die Chip

Pad R1 L1 Pin

DI---r---1c:=JI---Ic:=JI---r---ID

1 .

.70 to .80 18nH to 24nH

·1'

. C1 C2

T

^{Die Pad}

T

^{2.7pf t.o}

V

Capacitance

V

^3.7pf

Figure 6-1. 653 PackagelPin Electrical Model

114

The 650 Bridge Chip Set

6.4.2 654 Controller Model

The electrical model of the effects of package and pin parasitic effects on the 654 Controller is shown in Figure 6-2. The values shown are nominal values only, are not guar~nteed, and vary from pin to pin. Values lower than nominal are typical of pins located on the side of the package and which are closest to the chip. Values higher than nominal are typical of corner pins. Typical ranges are proportionally similar to those shown for the 653. Note that the total output capacitance of the die pad is derived by adding the value shown in Figure 6-2 (which is due to the package) to the value shown for DPC (Die Pad Capacitance) in Table 6-7 (which is due to the 1/0 book).

Die Pad

Wire Bond

R1 L1

.75Q 3nH

~.39PF

Lead Frame

R2 L2

.75Q 17nH

~.33PF

Figure 6-2. 654 PackagelPin Electrical Model

Chip Pin

~1.9PF C3

The 650 Bridge Chip Set

Dans le document PowerPC to PCI Bridge (Page 136-141)