,ill I AACK# ____
5.6 The pel to 650 Bridge Transactions
A read operation always returns a 64-bit double-word since system memory is a double-word bus (eight-byte data bus). PCLAD[2] is used to select between the high-order and low-order words within this double-word. Memory parity is checked based on a full double-word. (A parity error can occur if all of memory is not initialized prior to access.)
A PCI device can assert PCLFRAME# to initiate an address phase after the 654 Controller grants the address bus (either 10_BRDG_GNT# or one of the five PCLGNT lines) to the PCI device.
Successful completion of the PCI transaction results in
a
target ready (PCLTRDY#) asserted to the PCI device. Unsuccessful completion (memory out-of-range, parity error) results in a target abort (PCI_DEVSEL# deasserted and PCLSTOP# asserted), and an· error bit is asserted-MEM_PAR_ERR# for a parity error.If a parity error occurs during a PCI read of system memory, the 654 Controller asserts TRDY#, then drives incorrect (inverted) parity onto the PCLPAR line on the PCI clock after TRDY#, and then target aborts (PCLDEVSEL# deasserted and PCLSTOP# asserted). The 654 Controller asserts the MEM_PAR_ERR# signal and generates an interrupt to the 60X CPU; All subsequent PCI transactions to system memory from any agent are terminated with a target abort until after the 60X reads the error address register.
5.6.1 PCI to System Memory Cycles
• A PCI address from 2G to 2G + 256M translates to system memory from 0 to 256M.
• PCI memory read cycles from OG to 2G translate to 3G to 4G. These cycles cause snoop cycles but no hits because the 3G to 4G addres~ range is reserved as non-cacheable.
• Single or burst transfers are supported (PCI 2.0 specification compliant).
• From one to four bytes per beat are allowed (controlled by PCI byte enables).
5.6.1.1 1/0 Bridge to System Memory
• Supported by the 650 Bridge chip set if 1/0 bridge support exists.
• ISA_MASTER# pin allows special translation for ISA master addresses from 0 to 16M on the PCI bus.
5.6.1.2 ISA Master Memory Addressing
The 650 Bridge forwards PCI memory cycles which are the the result of an ISA bus master opera-tion to system memory. The ISA bridge asserts ISA_MASTER# and IO_BRDG_HOLD# to the 650 Bridge to indicate ISA bus master operations. .
Note: If the DMA produces an address in the 0 to 2G range without asserting ISA_MASTER#, a PCI cycle runs, but the 650 Bridge does not forward it to system memory because the address range is not 2G to 4G.
5.6.1.3 ISA Master Signal Timing
Figure 5-19 shows the timing relationships for ISA master operations.
98
The 650 Bridge Chip Set
FRAME#'
~ (~)---I.----t
,,----.---...----.----,;
1
TRDY#'
---f---"ll
(4)1,--.-________ _
IO_BRDG_GNT#,
1 ' - - - 1 _(3)1_ - - - - -... [;---1..._.:...--\1 NO_TRANS I ' _ - - L - _ . & . . - - - - L _ . . . I . . - - - - L _ ... _ _ I----'-_...L..---..L--If.
\1...-... _
Figure 5-19. ISA Master Signal Timing Notes for Figure 5-19:
1. 10_BRDG_HOLD# and ISA_MASTER# must be sampled asserted on the same clock for the 650 Bridge to recognize an ISA master transaction pending condition.
2. These transactions are mastered by the 650 Bridge or by a PCI buscmaster other than the 1/0 bus bridge.
3. When the ISA master transaction pending condition is recognized, the 650 responds to the next PCI transaction mastered by the 1/0 bus bridge as a PCI transaction on behalf of an ISA bus master. The 650 asserts NO_TRANS to disable the address translation that normally inverts the most significant address bit when a PCI bus mas-ter accesses system memory.
4. The arbiter grants the system to the 1/0 bus bridge.
5. This PCI transaction is mastered by the 1/0 bus bridge for the ISA bus master that has ISA bus mastership.
5.6.1.4 PCI to System Memory (DRAM) PCI_C/BE[3:0]# Bus Commands
Table 5-21 shows the PCI bus command decoding. When a PCI master has the PCI bus grant and asserts PCLFRAME#, the 654 Controller decodes PCLC/BE[3:0]# to determine if the PCI device is trying to access system memory. The 654 Controller maps PCI memory cycles with ad-dresses in the range of 2G to 4G as system memory (DRAM) reads and writes. The 650 Bridge only responds to PCI memory read and write cycles. All other cycles initiated by PCI devices on the PCI bus are ignored by the 650 Bridge.
If a memory cycle is decoded, the 654 Controller must determine if the translated memory address is in the range, from 0 to 2G, of system memory (DRAM). PCI devices address system memory with addresses from 2G to 4G. The 653 Buffer inverts PCLAD[31] to remap PCI addresses in the 2G to 4G· range to 0 to 2G.
The 650 Bridge Chip Set
The 654 Controller decodes the PC I bus address from the 60X CPU bus after the address is trans-lated by the 653 Buffer (PCLAD[31] is inverted). The 654 Controller initiates system memory (DRAM) cycles with snooping for addresses on the 60X CPU bus from 0 to 2G. For a 60X CPU bus address from 2G to 4G, the 654 Controller aborts the memory cycle. In this case, the snoop cycle is always a miss because addresses from 2G to 4G are reserved as not cacheable. (They must be marked non-cacheable in the 60X CPU).
Table 5-21. PCI Bus Commands from PCI Masters PCL C/BE[3 :0]# PCI Transaction Decoded as:
0000 Interrupt Acknowledge none
0001 Special Cycle none
0010 1/0 Read none
0011 1/0 Write none
0100 Reserved none
0101 Reserved none
0110 Memory Read memory read
0111 Memory Write memory write
1000 Reserved none
1001 Reserved none
1010 Configuration Read none
1011 Configuration Write none
1100 Memory Read Multiple memory read
1101 Dual Address ,Cycle none
1110 Memory Read Line memory read
1111 Memory Write and Invalidate memory write 5.6.1.5 Snoop Cycle Control Signals on the 60X CPU Host Bus
The 654 Controller maintains cache coherency with the L 1 and L2 caches by running snoop cycles on the 60X CPU bus for every PCI read or write to system memory, including burst transactions.
Section 5.7 describes the processing of snoop cycles in detail. To execute a snoop cycle, the 654 Controller asserts the following 60X CPU bus control signals:
• TBST# is negated
• TSIZ[0:2] (transfer size) is set to binary 100 (four bytes or one word).
• TT[0:3] (transfer type) is set to 01 01 b for snooping a read to system memory and to 0001 b for snooping a write to system memory.
The 60X CPU and a write-back L2 cache respond to a cache snoop hit by asserting ART RY#.
See Section 5.7 for a complete description of the processing of snoop cycles. The 650 Bridge asserts a target retry on the PCI bus when a cache device asserts ARTRY# for a cache hit. After
100
The 650 Bridge Chip Set
the cache completes its writeback, the 650 Bridge grants the bus to the original PCI device to retry the target retried transfer (if it is requesting the bus).