Decisions and branching are important parts of data proc-essing, and the programming methods by which these operations are carried out are important aspects of the programming task. The facilities offered by the System/360 are particularly powerful and flexible. The basic action is the setting of the condition code by any of a large number of instructions and the subsequent testing of the condition code by a Branch on Condition instruction.
Many arithmetic, shift, and logical instructions have as ~
part of their action the setting of the condition code to indicate something about the result of the instruction's execution. For instance, after an Add instruction, the condition code indicates whether the sum was zero, posi-tive, negaposi-tive, or too large for the register. After a Compare instruction the condition code indicates whether the first operand was greater than, equal to, or less than the second operand. The meaning of each of the different states or values of the condition code is specified in the descriptiop.
of each instruction that affects the code. These descriptions may be found in the System/360 Principles of Operation, which also contains a complete tabulation of the instruc-tions involved and the meaning of the condition codes.
The condition code occupies two bits (in the control program area of storage). Two bits can, of course, be set in just four ways: 00, 01, 10, and 11; and these four binary settings are equal to decimal values 0, 1, 2, and 3, respec-tively.
At any time after the condition code has been set by the action of an instruction, it may be tested by using a Branch on Condition (BC) instruction. In this instruction, which is in the RX format, the four bits that in other instructions designate a general register are here used for a mask that designates in which states of the condition code we wish a certain branch to occur.
The leftmost bit of the mask checks for a condition code of zero, the next bit for code 1, the next for code 2, and the rightmost for code 3. If the condition code is equal to any of the values selected by the mask bit(s), the Branch is taken. The correspondences between condition codes and mask are summarized in Table 3-1.
Note that the mask bits correspond from left to right with the four condition codes. Another way, perhaps easier to remember, of summarizing this correspondence is as follows:
Condition code Mask used to test code
0 2 3 8 4 2 1
A BC instruction with a decimal mask of 12 (8+4) specifies
that a branch is to be made if the condition code is
a
or 1, and is not to be made if the condition code is 2 or 3. A mask of 7 (4+2+1) will cause a branch only if the condition code is 1, 2, or 3.A decimal mask value of zero makes the instruction test for no condition codes; it thus becomes a no-operation instruction. A mask of 15 tests for any condition code; it is thus an unconditional branch.
Table 3-1. Masks for testing various states of the condition code Condition Mask bits Decimal value codes tested
0000
a
None0001 1 3
0010 2 2
0011 3 20r 3
0100 4 1
0101 5 1 or 3
0110 6 1 or 2
0111 7 1,2, or 3
1000 8 0
1001 9
o
or 31010 10
o
or 21011 11 0,2, or 3
1100 12
o
or 11101 13 0,1, or 3
1110 14 0,1, or 2
1111 15 0,1,2, or 3
A Sorting Procedure
To see how some of these ideas are applied, consider a simple example. We are given three fullword data items named A, B, and C. They may be positive or negative. We are required to change any negative values to positive, and then to rearrange the three values in storage to make the number in A the largest, the number in B the next largest, and the number in C the smallest of the three. Figure 3-14 expresses the logic of the method that will be used here to perform the sort; other ways are possible.
We first make all three numbers positive. A comparison is then made between A and B; if A is the smaller, we interchange the two values. Now we know that the value in A is the larger of the two, whether it originally was or not.
A similar process compares A and C and interchanges if A is smaller. Having done this, we know that what is in A is the largest of the three. A final comparison of the numbers now
Make A, B,C positive
A< B
Interchange A and B
A<C
Interchange Aand C
Interchange Band C
Figure 3-14. Program flowchart of a method of sorting three num-bers into descending sequence. Any negative numnum-bers are changed to positive before sorting.
40
in B and C, and an interchange if necessary, gets the
"middle" number in B and the smallest in C.
The program of Figure 3-15 involves some instructions that we have not used before. The Load Multiple (LM) instruction begins loading full words from the specified storage location. The first word goes into the fIrst-named register. Successive full words go into higher-numbered regis-ters until the second-named register has been loaded. In the program, the result of the LM instruction will be to place A in 2, B in 3, and C in 4.
Now three Load Positive Register (LPR) instructions change any negative numbers to positive, leaving any posi-tive numbers unchanged. This is an RR format instruction, meaning that both of its operands are registers. Here both operands are the same register, as will frequently be the case. The action is to take the value from a register, comple-ment it if it is negative, and place the result back in the same register. If it were necessary, two different registers could of course be used.
Next comes a Compare Register (CR) instruction, which is also in the RR format. This instruction does not change the contents of either register, but simply sets the condition code to zero if the two operands are the same, to 1 if the first operand is low, and to 2 if the first operand is high.
(The comparison is algebraic, meaning that signs are taken into account according to the rules of algebra, by which any positive number is greater than any negative number.
We know that our numbers are by now all positive, so this feature does not concern us.)
Next comes the Branch on Condition instruction, with a mask of 10 (decimal) and a branch address of COMP2. The mask of 10, checking with the table above, tests for condi-tion code zero or 2. Following a Compare-type instruccondi-tion, these mean, respectively, that the first operand is equal to or greater than the second operand. If the condition code is either of these, we branch; otherwise the next instruction in sequence is taken. The effect is: if the number in register 2 is already equal to or greater than the number in register 3, we skip down to the second comparison, because A and B are already in correct sequence.
The interchange, if it is necessary, is performed by moving the contents of register 2 to register 6, moving 3 to 2, and finally moving 6 to 3. These transfers are made with the Load Register (LR) instruction.
The remaining instructions repeat these operations twice for the other comparisons. Finally, there is a Store Multiple (STM) instruction to place the rearranged items back in the original three locations, as required by the problem statement.
Figure 3-16 shows before-and-after values of A, B, and C for six possible original orderings of the three values. Each pair of lines is one set. These are hexadecimal numbers; the original value of A in the last set is -3.
LOC OBJECT CODE ADDRI ADDR2 STMT SOURCE STATEMENT
1 PRINT NOGEN
000100 2 SORT START 256
000100 05BO 3 BEGIN BALR 11 ,0
000102 4 US!NG *,11
000102 9824 B036 00138 5 LM 2,4, A LOAO REGISTERS WITH 3 NUt-1BE~S
000106 1022 6 LPR 2,2 MAKE NUMBERS POSITIVE
000108 1033 7 LPR 3,3
00010A 1044 8 LPR 4,4
00010C 1923 9 C~ 2,3 COMPARE A AND B
00010E 47AO B016 00118 10 BC 10,COMP2
000112 1862 11 LR 6,2 INTERCHANGE IF NECFSSARY
000114 1823 12 LR 2,3
000116 1836 13 LR 3,6
000118 1924 14 COMP2 CR 2,4 COMPARE A AND C
00011A 47AO B022 00124 15 BC 10,COMP3
00011E 1862 16 LR 6,2 INTER.CHANGE IF NECFSSARY
000120 1824 17 LR 2,4
000122 1846 18 LR 4,6
000124 1934 19 COMP3 CR 3,4 COMPARE BAND C
000126 47AO B02E 00130 20 BC 10, OUT
00012A 1863 21 LR 6,3 INT ERCHANGE IF NECESSARY
00012C 1834 22 LR 3,4
00012E 1846 23 LR 4,6
000130 9024 8036 00138 24 OUT STM 2,4,A STORE SORTED VALUES
25 EOJ
000136 0000
000138 00000001 28 A OC F' 1 '
00013C 00000002 29 B DC F' 2'
000140 00000003 30 C DC F' 3'
000100 31 EI\JD BEGIN
Figure 3-15. Assembly listing of a program to carry out the sorting procedure charted in Figure 3-14
INPUT1 00000001 00000002 00000003 OUTPUT1 00000003 00000002 00000001 INPUT2 00000001 00000003 00000002 OUTPUT2 00000003 00000002 00000001 INPUT3 00000002 00000001 00000003 OUTPUT3 00000003 00000002 00000001 INPUT4 00000003 00000002 00000001 OUTPUT4 00000003 00000002 00000001 I NPUT5 00000003 00000001 00000002 OUTPUTS 00000003 00000002 00000001 INPUT6 FFFFFFFD 00000002 00000001 OUTPUT6 00000003 00000002 00000001
Figure 3-16. Six sets of sample input and output for the program of Figure 3-15