ADSP-3128A
J
Grades K Grades S Grades' T Grades'o
to +70·Co
to +70·C -55 to + 125·C -55 to -125·CParameter Min Max Min Max Min Max Min Max Unit
tL Clock LO Period 20 ns
tH Clock HI Period 22 ns
tcs Control Setup 10 ns
tCH Control Hold 1 ns
tAsTR Transparent Address Setup - Read 18 ns
tASTW Transparent Address Setup - Write 30 ns
tASRR Registered Address Setup - Read 4 ns
tASRW Registered Address Setup - Write 11 ns
tAH Address Hold 3 ns
tENA Three-State Enable Delay 2 21 ns
tDIS Three-State Disable Delay 11 ns
tDISBS Three-State Disable Delay - Bank & Port Sel 24 ns
tODTT Trans Adr-to-Trans Output Delay 39 ns
tODe Clk-to-Data Output Delay - C & Dports 18 ns
tODRT Clkd Adr-to-Trans Output Delay 40 ns
tODH Output Data Hold 3 ns
tDSR Latched Data Setup 7 ns
tDST Transparent Data Setup 18 ns
tDSN Clock-on-Falling Data Setup 12 ns
tDH Input Data Hold
1
c c nsWrite Enable Setup
-
< c c c Cia
tWEN ns
tWIN Write Inhibit Delay '0 ns
tATBE Trans Adr to Write Enable 1 ns
tWINH Write Inhibit Control Hold Time 0
NOTES
1 All min and max specifications are over power-supply and temperature rlU'ige indicated. Input levels are GND and 3.0V. Rise times are Sns. Input timing reference levels and output reference levels are 1.5V, except for tENA, tDIS arid tmsBs which are as indicated In Figures 3, 12 and 13.
's
and T grade parts are available processed in accordance with MIL-STD-883, Class B. The processing and test methods used for S/883B and T/883B versions of the ADSP-3128A can be found in Analog Devices' Military Data Book. Regnlar S and T grade parts are tested at + 125°C.'Worst-case with all outputs switching twice per cycle. (Example: DP Reads) Spec.tfications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage . . . -0.3V to +7V Input Voltage . . . -0.3V to VDD +0.3V Output Voltage Swing . . . -O.3V to VDD +O.3V Operating Temperature Range (Ambient) . . . . -SS·C to +125°C Storage Temperature Range . . . -65°C to + 150°C Lead Temperature (JOsec) PGA . . . +300°C
*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximwn rating conditions for extended periods may affect device reliabilIty.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
3-58 MICROCODED SUPPORT COMPONENTS
ADSP-3128A
ESD SENSITIVITY _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The ADSP-3128A features proprietary input protection circuitry. Per Method 3015 of
MIL-STD-883C, the ADSP-3128A has been classified as a Class 1 device.
Proper ESD precautions are strongly recommended to avoid functional damage or perfor-mance degradation. Charges as high as 4000 volts readily accumulate on the. human body and test equipment and discharge without detection. Unused devices must be stored in conductive foam or shunts, and the foam should be discharged to the destination socket before devices are removed. For further information on ESD precautions, refer to Analog Devices' ESD Prevention Manual.
INPUT OUTPUT
3pF
Equivalent Input Circuits Equivalent Output Circuits
','TO 00UTPUT
PIN
WARNING! 0
~~D'V<Cl
'01.
+15V
Normal Load for
ac
MeasurementsThis information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
MICROCODED SUPPORT COMPONENTS 3-59
Clock
Rlltran Control
Transparent CIOIE Read Addresses
Clocked Read Oat
Clocked ClO/E Read Addresses
Transparent Read Data
Clocked Read Data
:
1-
'L---I;
IH--1
. RAM READ RAM WRITE .... I_R_A_M_R_E_AD-j
!
phase exI
{Jhase~ !
phase rI I I
I I I
,~~~:~_ I !
'.01 I I
"-.:"'~,:::,1",::,- I I
Figure 4. ADSP-3128A Single-Precision Read Output Timing
Reads
Transparent Address
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
3-60 MICROCODED SUPPORT COMPONENTS
Clock
Double-Precision (DP) Control
Latched AlBIE Write Addresses
Transparent AlBIE Write Addresses
Latched Write Data
Transparent Write Data
ABltlEIt=1 ABhtlEht=1
Clock-an-Falling Write Data
ABltlEIt.O.
ABhtlEht=O l
Write Inhibit (LO for enable) (AlB/Ewinh)
Write Inhibit (HI for inhibit) (AlB/Ewinh)
phase (l phase
P
phase Y}=:): )(
)(}: }(
::{}= ::{
ADSP-3128A
Controls for All Modes
Addressing Modes
Write Data
Write Enable and Inhibit
Figure 5. ADSP-3128A Single-Precision Write Input Timing
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
MICROCODED SUPPORT COMPONENTS 3-61
~----~~--- - ~ - - -
-~ tH ~ tl --+!f-' - - - - 1 Clock
Double·PreCISlon (DP) Control
Latched Write Data to Hold
Transparent Wnte Data I
to Hold Transparent ABIVEI'='!
WnteHD,dataCJock-on_Fallmg ABltlElt .. O
!
to 0 ABhtlEht=O :
,
Latched Write Data,
I nput Latch Contents
Hold to
Clock-on-Fallmg A8ItJElt=O I
, ,
Figure 6. ADSp·3128A Single-Precision Write to Input Latches and Hold Timing, ,
This information appltes to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
3-62 MICROCODED SUPPORT COMPONENTS
Clock
Double-Precision (DP) Control
Clocked CIDIE Read Addresses
CDtranlEtran
Early Double-Precision Read
CDtranlEtran
Late Double-Precision Read
Transparent CIDIE Read Addresses
CDtranlEtran
Early Double-PrecIsion Read
CDtranlEtran
Late Double-Precision Read phase ex.
, , , ,
Radtrn=1
! !
RAM READ
phase phase Y
Figure 7. ADSP-3128A Double-Precision Read Output Timing