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ADSP-21 01 IADSP-21 02

Dans le document Floating-Point Components • (Page 64-75)

but has no bit-reversal capability. Both DAGs can also be u,cd for serial port autobuffering.

There are three register files in each DAG: the modify (M) reg-ister file, the index (I) regreg-ister file and the length (L) regreg-ister file. Each of these register files contains four l4-bit regi,ters which are readable and loadable from the DMD bus. The I reg-isters hold the actual addresses used to access external memory.

When using the indirect addressing mode, the selected I register content is driven onto either the PMA or DMA bus. This value is post-modified by adding the (signed) contents of the selected • M register. The modified address is passed through the modulus logic.

Associated with each I register is an L register which contains the length of the buffer addressed by the I register. The L regis-ter and the modulus logic together enable circular buffer ad-dressing with automatic wraparound at the buffer boundary.

Automatic wraparound is also used by the serial ports to gener-ate the serial port interrupt when operating in auto buffering mode. The modulus logic is disabled by setting the L register to

zero.

PMD.I>MD Bus Exchange

The PMD-DMD bus exchange circuit couples the PMD and DMD buses. The PMD bus is 24 bits wide and the DMD bus is 16 bits wide. The upper 16 bits of PMD are connected to the DMD bus. An 8-bit register (PX) allows transfer of the full width of the PMD bus. When data (as distinct from an instr\w-tion) is read from the PMD bus, the lower 8 bits of the PML>

bus are 1000ded into PX. When writing to the PMD bus, the C<lntents of PX are appended to the upper 16 bits, forming a 24-bit value. The PX register is also readable and loadable from the DMD bus.

Program Sequencer

The program sequencer incorporates powerful and flexible mechanisms for program flow control such as zero overhead looping, single cycle branching (both conditional and uncondi-tional) and automatic interrupt processing. Figure 6 shows a block diagram of the program sequencer.

Figure 6. ADSP-2101 Program Sequencer This information applies to a product under development. Its characteristics and sp~cifications ar~ sUbi.e.ct to change without notice.

Analog Devices assumes no obligation regarding future manufacture unless otherWise agreed to In writing.

DSP PROCESSORS 2-57

The sequencing logic controls the flow of the program execu-tion. It outputs a program memory address onto the PMA bus from one of four sources: the PC incrementer, PC stack, instruction register or interrupt controller. The next address source selector controls which of these four sources are selected based on the current instruction word and the processor status.

A fifth possible source for the next program memory address is provided by DAG2 when a register indirect jump is executed.

The program counter (PC) is a 14-bit register which contains the address of the currently executing instruction. The PC output goes to the incrementer. The incremented output is selected as the next program memory address if program flow is sequential.

The PC value is pushed onto the 16 x 14 PC stack when a CALL instruction is executed or when an interrupt is processed. The PC stack is popped when the return from a subroutine or inter-rupt is executed. The PC stack is also used in zero overhead looping.

The program sequencer section contains six status registers.

These are the Arithmetic Status register (ASTAT), the Stack Status register (SSTAT), the Mode Status register (MSTAT), the Interrupt Control register (ICNTL), the Interrupt Mask reg-ister (IMASK) and the Interrupt Force and Clear regreg-ister (IFC).

Interrupts

The interrupt controller allows the processor to respond to the six possible interrupts with a minimum of overhead. Individqal interrupt requests are logically ANDed with

the bitS

ip IMASK; , the highest priority unmasked interrupt i., then select~d. ' The interrupt control register, ICNTL;'alloW!l each interrupt to "

be set as either edge or level sensitive. DependinJ

OIi,

a bidn ICNTL, interrupt routines can either be nested with higher

pri-ority interrupts taking precedence or processed sequentially with ' only one interrupt service active at a time.

The 12-bit interrupt force and clear register, IFC, contains a force bit and a clear bit for each of the six possible interrupts.

When responding to an interrupt, the status registers ASTAT, MST AT, IMASK are pushed onto the status stack and the PC counter is loaded with the appropriate vector address. The sta-tus stack is seven levels deep to allow interrupt nesting. The stack is automatically popped when a return from the interrupt is executed.

The vector addresses for each interrupt are fixed. In the ADSP-2101 each vector location identifies a block of four instructions.

Short service routines can be executed without an additional JUMP, minimizing overhead.

IMASK

IMASK is six bits wide and allows the interrupt inputs to be individually enabled or disabled. The bits in IMASK are:

o

Timer interrupt enable

I IRQO or SPORT I receive interrupt enable 2 IRQI or SPORTI transmit interrupt enable 3 SPORTO receive interrupt enable 4 SPORTO transmit interrupt enable 5 IRQ2 interrupt enable.

The bits are all positive sense (0 = disabled, I = enabled).

IMASK is set to zero upon a processor reset so that all inter-rupts are disabled initially.

ICNTL

ICNTL is a 5-bit register configuring the interrupt modes of the processor. The bits in ICNTL are:

The sensitivity bits determine whether a given interrupt input is edge- or level-sensitive (0= level-sensitive, I = edge-sensitive).

The interrupt nesting mode determines whether nesting of inter-rupt service routines is allowed. When set to zero, all IMASK bits are automatically set to zero when an interrupt service rou-tine is entered. Previous IMASK values are pushed on the stack. When set to one, IMASK is set so that equal and lower priority interrupts are masked, permitting higher priority inter-rupts to interrupt the current interrupt service routine.

Edge-triggered interrupts are automatically cleared when the interrupt service routine is called. They can also be cleared by writing a one to the apprqprjate IFC bit.

The timer and serial'port

f~rruPts

act as edge-sensitive inter-rupts which can be masked, 'cleared or forced with software. If y~

force.a

level-sensitive interrupt in software, it is

automati-cally

cleared. For proper operation, the SPORT! sensitivity bits must be set tocedge-sensitive.

Il'C

SPORTI receive or IRQO interrupt clear SPORTI transmit or IRQI interrupt clear SPORTO receive interrupt clear SPORTO transmit interrupt clear IRQ2 interrupt clear

Timer interrupt force

SPORT! receive or IRQO interrupt force SPORT I transmit or IRQI interrupt force SPORTO receive interrupt force SPORTO transmit interrupt force IRQ2 interrupt force.

Pending edge-sensitive interrupts can be cleared by writing a one to the appropriate clear Bit (0-5) in IFC. Edge-triggered interrupts are normally cleared automatically when the corre-sponding interrupt service routine is called.

Interrupts can be forced under program control by writing a one to the force Bit (6-11) corresponding to the desired interrupt.

This causes the interrupt to be serviced once, unless masked.

The timer and SPORT interrupts behave like edge-sensitive in-terrupts and can be masked, cleared and forced.

Loop Mechanisms

The DO UNTIL instruction executes a zero overhead loop us-ing the loop stack and the loop comparator. For a DO UNTIL instruction, a 14-bit termination address and a 4-bit termination condition are pushed onto the 18-bit loop stack. The address of the next instruction (which identifies the top of the loop) is pushed onto the PC stack. The loop comparator continuously

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.

2-58 OSP PROCESSORS

compares the current PC value against the termination address on the top of the loop stack. When the termination address is detected, the processor checks if the termination condition is met. If the termination condition is not met, then the top of the PC stack is used as the next PC address, returning program flow to the beginning of the loop. If the termination condition is met, then the PC stack is popped, the current PC is incremented by one and program flow falls out of the loop. The loop stack is four levels deep, permitting four levels of zero overhead loop nesting.

The down counter and the count stack also support this power-fullooping mechanism. The down counter is a l4-bit register with auto decrement capability. It is loaded from the DMD bus with the loop count. The count is decremented every time the counter value is checked; when the count expires, the counter expired (CE) flag is set. The count stack allows the nesting of loops by storing temporarily dormant loop counts. When a new value is loaded into the counter from the DMD bus, the current counter value is automatically pushed onto the count stack, as program flow enters a loop. The count stack is automatically popped whenever the CE flag is tested and is true, thereby resuming execution of the cod~ outside the loop. "

Status Registers ' ", J',

The ADSP-2101 maintains six sta~lluellst'll"s,,;.mlch,~ be' accessed over the DMD bus (one ~,*~nlt

md

one i,s

Interrupt Force and Clear. (Write-On(y) The interrupt registers are described in a previous section; the other three are discussed below.

ASTAT

,:,

ASTAT is 8 bits wide and holds the status information gener-ated by the computational sections of the processor. The bits in ASTAT are defmed as follows:

o AZ

(ALU Result Zero) automatically updated when a new status is generated by the arithmetic operations affecting them, as defmed by the following table:

Any ALU operation except division ALU absolute value operation ALU divide operations

Any MAC operation except saturate MR Shifter exponent detect operation.

ADSP-21 01 IADSP-21 02

SSTAT

5

Status Stack Overflow 6 Loop Stack Empty 7 Loop Stack Overflow.

All of the bits are positive sense (1 = true, 0 = false). The empty status bits indicate that the stack is empty. The overflow status bits indicate that the stack has overflowed. Since the stack over-flow status bits "stick" once they are set, subsequent pop opera-tions have no effect on them. This means that the stack can be both overflowed and empty under certain circumstances. A pro-cessor reset or a softWl\I'O- reboot must be executed to clear the stack ovedlow

'jItBtUs. '

, " i ' '

MSTAT" ,,,"

" MST'AT

is a ?-bit register that defines various operating modes ''of the procesS9l'. TlIe mode control instruction enables or

dis-ables tb~ ci!>e~l'QOdes. The bits in MSTAT are:

.r- .:- 'N'~ ,

, , 0: ':,Pm

-Register Bank Select

, I""

Bit-Reverse Mode (DAGl Only)

2 AtU,Overflow Latch Mode 3 AR.Saturation Mode

4 MAc

Result P Placement Mode

5

Timer Enable

6 Go Mode.

The data register bank select bit determines which set of data registers is currently active (0

=

primary, I

=

secondary). The data registers include all of the result and input registers to the ALU, MAC and shifter (AXO, AXI, AYO, AYI, AF, AR, MXO, MXI, MYO, MYI, MF, MRO, MRI, MR2, SB, SE, SI, SRO and SRI). At RESET, the data register bank select bit is cleared.

The bit-reverse mode, when enabled, bit-wise reverses all ad-dresses generated by DAG 1. This is most useful for reordering the input or output data in a radix-2 FFT algorithm.

The ALU overflow latch mode causes the AV (ALU overflow) status bit to "stick" once it is set. In this mode, when an ALU overflow occurs, AV will be set and remain set, even if subse-quent ALU operations do not generate overflows. AV can then only be cleared by writing a zero into it from the DMD bus.

The AR saturation mode, when set, causes ALU results to be saturated to the maximum positive (H#7FFF) or negative (H#8000) values when an ALU overflow or underflow occurs.

The MAC Result

P

Placement bit, when set to 0, results in the ADSP-2100 result placement of the multiplier product in the MR register (one bit shift). When this bit is I, no shift occurs.

The Timer Enable bit, when set to I, enables the timer decre-ment mechanism.

The Go Mode bit, when set to I, allows the processor to con-tinue operations internally (when possible) while the external address and data buses are tristated during a bus grant.

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.

DSP PROCESSORS 2-59

- - - -

-~-CONDITION CODES

The condition codes are used to determine whether a conditional instruction, such as a jump, trap, call, return, MAC saturation or arithmetic operation, is performed. The 16 basic composite status conditions and their derivations are shown in Table II.

Since arithmetic status is latched into AST AT at the end of a processor cycle, the condition logic represents conditions gener-ated on the previous cycle. ALU Less Than Zero ALU Greater Than or Equal

Signal Name Function SCLK Receive Frame Synch 1/0 Transmit Frame Synch 1/0 Serial Data Receive Serial Data Transmit,

Here is a brief list of the capabilities of the ADSP-2101 SPORTs. Figure 7 shows a simplified block diagram of a single SPORT.

• Bidirectional: each SPORT has a separate transmit and re-LE ALU Less Than or Equal

• Double buffered: each SPORT section (both receive and transmit) has a data register accessible to the user and an internal transfer register. The double buffering provides additional time to service the SPORT.

GT ALU Greater Than Zero AV) ALU X Input Sign Positive Not Counter Expired ,',

In addition to the basic 16 conditions, the JUMp"and CALL instructions also support the use of the FI pin as a conditional :-. ,

Table III. Additional Condition Codes For JUMP and CALL Timer

A programmable interval timer can generate periodic interrupts.

When the decrementing mechanism is enabled, a 16-bit count register (TCOUNT) is decremented every

n

cycles, where n-l is a scaling value stored in an S-bit register (TSCALE). When the value of the count register reaches zero, an interrupt is gener-ated and the count register is reloaded fl'9m a 16-bit period reg-ister (TPERlOD). Timer interrupts can be masked, cleared and forced in software if desired.

The ADSP-2101 S-bit prescaler allows periodic interrupts over a wide range of possible times. In a processor with an sOns cycle time, for example, the timer interrupt could occur as infre-quendy as every 1. 34 seconds if a maximum scaling value is used. With a minimum scaling value a maxim\llll period of 5.24ms can be timed.

SERIAL PORTS

The ADSP-2101 incorporates two complete serial ports (SPORTO and SPORTl) for serial communications and multi-processor coordination.

• Flexible clocking: each SPORT can use an external serial clock (up to the fu}l~ .. sor cycle rate) or generate its own (from 94Ha up

to

olle

hidf

the processor cycle rate).

• F1taibICl

f~:

:eadt SroRT section (receive and transmit) CIiIn fUll

in

an unframed mode; with internally generated or ftl;emally generllted ~e synch signals; with active high or inverted frame ~sl:_ either of two pulse widths!

". ~.'FrlUll'li.g for the receive and transmit sections is ,~" . independent but shares the same serial clock.

' . Flexibj,e VI'\)l'Q length: each SPORT supports serial data word , Jed!!. f~ ~ee to sixteen bits.

• Companding in hardware: each SPORT provides optional A-law and ....-law companding according to CCITT recommen-dation G. 711. Different companding can be used for each SPORT, for example, A-law for SPORTO and .... -law for SPORT 1.

• Flexible interrupt scheme: each SPORT section (receive and transmit) can generate a unique interrupt upon completing a data word transfer or after transferring an entire buffer (see next item).

• Autobuffering with single cycle overhead: using the ADSP-2101 DAGs, each SPORT can receive andlor transmit an en-tire circular buffer of data with an overhead of only one cycle per data word. Transfers to and from the SPORT and the circular buffer are automatic in this mode and do not require additional programming. An interrupt is generated only when pointer wraparound occurs in the circular buffer.

• Multichannel capability: SPORTO provides a multichannel interface for selective receipt and transmission of arbitrary data channels from a 24- or 32- word, time division multi-plexed, serial bitstream. This is especially useful for Tl or CEPT interfaces or as a network communication acherne for multiple processors.

• Alternate configuration: SPORTI can be configured as two extemal interrupt inputs (IRQO and IRQl) and the Flag In and Flag Out signals. The internally generated serial clock may still be used in this configuration.

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.

2-60 DSP PROCESSORS

Figure 7. Serial Port Block Diagram SPORT OPERATION

Each SPORT has a receive and a transmit register; SPORTO's registers are RXO and TXO; SPORTl's are RXI and TXI.

Companding (a contraction of COMpressing and exPANDing) is the process of logarithmically encoding data to minimize the number of bits that must be sent. Both SPORTs share the

_.r-panding hardware: one expansion and one comptes$lon opera-"'1'/

tion can occur in each processor cycle, ,l!hhe ~ent

l:if

{lOdten-tion, SPORTO has priority. The "DSP~Z101.stipp()rts both~f

I

Clock or C~al

r

" "

ADSP-21 01/ADSP-21 02

the widely used algorithms for companding: A-law and ....-law.

The type of companding can be independently selected for each SPORT.

The TXn and RXn registers are identified by name in the ADSP-2101 assembly language, not memory-mapped. TXn and RXn can be read and written (like other non-data registers) with the following instructions: read/write to data memory (direct address), load non-data immediate, and internal (register-to-register) moves. They cannot be accessed by instructions that require indirect addressing, i.e., addresses generated by the DAGs.

There are two ways to generate the SPORT interrupts after the transmission or receipt of (1) each data word or (2) each com-plete buffer of data words.

Normal (Word by Word) Operation

Writing to the TXn register readies the SPORT for transmis-sion; the TFS silw;lllW.tes it. The value in TXn is shifted into t~e iQJernat, J;I13nsnltt, register, and after framing

synchroni-; ~If~~:o~~d<synchroni-;if required), the bits are sent, MSB first.

\Wh~fi.ifirst

bit.s been transferred, the SPORT generates ithe"tranJli9it i~u •. TXn is now available for the next

~C9 Qf; data, ~Jli'oUgh the transmission of the first is not

;;'\'I;~P1e\.,,:r r, ',- '/';:'2'ir 'j,' ,,~

~ T: f

'"

.~ '~'"

, ,1,

. -,

elKIN XTAL ClKOUT Ai~o /' GND ~~ "FS

SERIAL TFS Senal Device

--<0 RESET PORT 0 DT

--<0 IRQ2 (Optional)

ADSP-2101

DR

--<0 BR

--

8G MMAP SERIAL RFS TFS SCLK or or i"IRf'f IAOO Senal Device

--<0 PORT 1

OT or FO PMS AOWR ADDRESS DATA ~ fm DR or FI

, . , 2.

2* ,. , 'ye

A D CS A D CS A D n

(Option, I) PROGRAM MEMORV

Oe Oe OE

WE WE BOOT

EPROM

(Opt/on.') 2764

DATA 27128

MEMORV 27256

8 27512

PERIPHERALS

250"1

NOTE: The two MSSI ot thl Boot EPROM Add ... are 11.0 the two MSI. ( of the Data lUI. Thll II only requl ... d for the 27258 and 27512.

The eight data bit. of thl Boot Memory Spice cor .... pond to D 15-8 The Ilxt.en date bit. 01 the Da'i Mlmory SPICI cor .... pond to D23_,

Figure

8.

ADSP-2101 Basic System Configuration

(OpflOnlJl)

D 23, 22 )

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.

DSP PROCESSORS 2-61

In the receiving section, bits accumulate as they are received in an internal receive register. When a complete word has been received, it is shifted into the RXn register and the receive

In the receiving section, bits accumulate as they are received in an internal receive register. When a complete word has been received, it is shifted into the RXn register and the receive

Dans le document Floating-Point Components • (Page 64-75)