Simulations and Results

This paragraph collects the results of simulations carried out on the project of the keyboard scanning implementation. The measurements were related to

• The duration of a full scan of the keyboard.

• The length of the ELF (Executable Linkable Format) file generated by the C code compilation.

During the analysis it was possible to change the value of some parameters:

• The type of algorithm being used: standard or optimized.

• The scan reading method: once or voting.

• Data buffer insertion: enabled or disabled.

The different combinations of parameters of the scanning algorithm are shown in the following Table9.1.

The setup used to perform the different measures is reported in the following Fig.9.6.

With respect to both the total time required for the scanning routine and the size of theELFfile the compilation option ‘-oS’ resulted to be the best, even if only slightly, provided that the debugging symbols are not included, as shown in Fig.9.7. This parameter has been chosen for the execution of the performance tests that follow. A comparison of the eight algorithm combinations as been performed for different frequencies of the MicroBlaze clock: 33, 50, 66 and 100 MHz.

From the data obtained, shown in Fig.9.8, it is possible to say that the per-formance using a clock of 50 MHz is not acceptable because, in the perspective of implementing the keyboard scanning task in a multiprocessor system using a scanning period of 200ls, the time the CPU is occupied is so high that it impossible to do anything else between a scan and the next. The performance

Table 9.1 Different scanning algorithm combinations

Combination Algorithm Scan reading method Buffer

Comb1 Standard Once Disabled

Comb2 Standard Once Enabled

Comb3 Standard Voting Disabled

Comb4 Standard Voting Enabled

Comb5 Optimized Once Disabled

Comb6 Optimized Once Enabled

Comb7 Optimized Voting Disabled

Comb8 Optimized Voting Enabled

130 M. Caldari et al.

obtained with a 100 MHz system clock are surely the best among the considered cases, however, it is important to remember that higher frequencies may create more problems with respect to electromagnetic compatibility issues.

A further analysis was performed to derive the percentage of occupation of the MicroBlaze computing power during the execution of the keyboard scanning task repeated every 800ls.

Fig. 9.6 Block diagram of the measurement setup

Fig. 9.7 Executable.elf file length variation with respect to different compilation options

Fig. 9.8 Scanning time at different microblaze clock frequencies

9 A Multiprocessor Platform for Efficient Data Processing 131

This measure, whose results are presented in Fig.9.9, is very important to understand the availability of the microcontroller to perform additional functions, possibly provided by the main processor.

In conclusion two types of scanning algorithms have been taken into account, the standard and the optimized one. The second was built on the optimization of the initial standard. In the analysis of performance several compilation options were tested and the more efficient ‘-oS without debug symbols’ allows a reduction of about 20% of the execution time of the scanning routine scan and a reduction of about 30% on code size, with respect to the option ‘-o1 with debug symbols’.

Regarding the size of the ELF file the results indicate that among the eight variations considered for the scanning algorithm, there are no remarkable differ-ences and the binary file length is around 45 Kbytes for both the standard and optimized algorithms.

Significant results were obtained for the timing parameter. Using the algo-rithms implemented in this work, to obtain a scanning routine duration of less than 200ls, MicroBlaze should be provided with a clock frequency of more than 33 MHz; in fact using a 50 MHz clock the minimum scanning routine duration corresponds to around 193.6ls. In case this application is going to be executed with a scan period equal to 200ls too little time remains to serve other tasks possibly assigned by the main processor; using a clock frequency of 66 or 100 MHz performance obviously increase significantly. These results show that it is possible to continue the research on a multiprocessor structure in which each processing element may execute different tasks assigned by the main controller.

Fig. 9.9 Microblaze percentage occupation during a scan period of 800ls

132 M. Caldari et al.

9.5 Conclusion

In this paper a preliminary work was presented regarding a multiprocessor architecture for the efficient processing of applications for electronic musical instruments. This activity is still incomplete, but nonetheless some projects were completed in order to understand some key elements of the architecture as the strategy of communication between processors and their maximum achievable performance. The results obtained so far are quite interesting and the search will continue to integrate all elements of the architecture and to test it with real traffic conditions generated by different kind of applications.

References

1. Xing J, Zhao W, Hu H (2008) An FPGA-based experiment platform for multi-core system.

In: The 9th international conference for young computer scientists, 18–21 November 2008, pp 2567–2571

2. Gao RX, Fan Z (2006) Architectural design of a sensory node controller for optimized energy utilization in sensor networks. IEEE Trans Instrum Meas 55(2):415–428

3. Maslennikov O, Shevtshenko J, Sergyienko A (2002) Configurable microcontroller array. In:

Proceedings of the international conference on parallel computing in electrical engineering, pp 47–49

4. Marton L (2008) Distributed controller architecture for advanced robot control. In:

International symposium on industrial electronics, 30 June 2008–2 July 2008, pp 1412–1417 5. Kim S-H, Seo S-H, Kim J-H, Moon T-M, Son C-W, Hwang S-H, Jeon JW (2008) A gateway system for an automotive system: LIN, CAN, and FlexRay. In: 6th IEEE international conference on industrial informatics, 13–16 July 2008, pp 967–972

6. Wobschall D, Prasad HS (2002) Esbus—a sensor bus based on the SPI serial interface. In:

Proceedings of IEEE sensors vol 2. pp 1516–1519

7. Cucej Z, Gleich D, Kaiser M, Planinsi P (2004) Industrial networks. In: Proceedings of the 46th international symposium electronics in marine, 16–18 June 2004, pp 59–66

8. Paggi G, Ortolani M, Gigli S, Conti M, Caldari M, Ripa F (2009) Development of a multiprocessor architecture for efficient processing allocation in electronic musical instruments. In: Proceedings of the IEEE 7th international workshop on intelligent solutions in embedded systems WISES09 Ancona, Italy, June 2009, pp 79–86

9. Berekovic M, Heistermann D, Pirsch P (1998) A core generator for fully synthesizable and highly parameterizable RISC-cores for system-on-chip designs. In: IEEE Workshop on signal processing systems, 8–10 October 1998, pp 561–568

10. Hempel G, Hochberger C (2007) A resource optimized processor core for FPGA based SoCs.

In: 10th euromicro conference on digital system design architectures, methods and tools, 29–31 August 2007, pp 51–58

11. Gschwind M, Salapura V, Maurer D (2001) FPGA prototyping of a RISC processor core for embedded applications. IEEE Transac Very Large Scale Integr Syst 9(2):241–250 12. MicroBlaze core, seehttp://www.xilinx.com

9 A Multiprocessor Platform for Efficient Data Processing 133

Chapter 10

A Distributed Hardware Algorithm