Gas Leak Detection Case Study in H 2 Vehicles
5.5 Embedded ISIF Design and Realization
To fast identify, trim and verify at experimental level an architecture to interface and compensate a given sensor, a mixed-signal embedded hardware platform for Intelligent Sensor Interface (ISIF) has been developed by University of Pisa in collaboration with SensorDynamics AG [14]. Realized in 0.35lm BCD (Bipolar CMOS DMOS) technology with 3.3 V supply for the digital part and 5 V for the analog one, the IC has been developed according to a platform based design strategy [15], by assembling a set of analog, digital and software intellectual property (IP) modules in the same multi-channel sensor interfacing chip.
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The architecture of the mixed-signal embedded system is sketched in Fig.5.8. It is composed of an analog front end and a digital processing section with a JTAG standard interface between the two signal domains. The basic idea behind the architecture in Fig.5.8is using a low-cost sensor and reducing to a minimum the analog signal processing, while compensating non-ideality through digital signal conditioning, since digital circuitry can be easily designed and scaled in micro-electronics technologies. The analog front-end in Fig.5.8 mainly accomplishes tasks of driving sensor’s electrodes (in case of sensor requiring external excita-tions), through couples of thermometer-type DACs and performing signal acqui-sition by means of SAR-type ADCs and programmable-gain operational amplifiers. It also provides a regulated power supply to the digital section. All modules are digitally controlled since gain coefficients, offset values and reference voltages are set by means of dedicated registers accessed via the JTAG bridge by the digital processor. Hence, also the analog part is configurable while the digital part is both HW-configurable and SW-programmable. The default HW configu-ration plane and the TEDS can be stored in on-chip PROM. All non-trivial signal processing required for sensor conditioning, i.e. filtering, function generation and demodulation, is performed by the digital section which also monitors system activity and handles communication with external devices. Both dedicated and general purpose computing resources are available in the digital part for a good trade-off between power consumption and flexibility. The HW DSP chain in Fig.5.8contains dedicated circuits for digital signal processing: FIR/IIR filters to remove noise/interference sources and a digital Phase Locked Loop (based on numerically controlled oscillators) for demodulating the sensor response and for function generation (e.g. sensor stimuli) based on the direct digital synthesis concept. General purpose tasks are managed by CPU core provided in a config-uration with on-chip program/data memories and standard parallel I/O plus UART and SPI interfaces for communication. In this system the CPU core is in charge of monitoring the DSP chain and managing communication/control flows among the mixed-signal part via JTAG, the DSP unit, the internal memories and the external devices. This basic architecture has been implemented in silicon in two configu-rations where the main differences are the used CPU core and the amount of on-chip memory resources. The first configuration in Fig.5.8a is based on a
CPU
JTAG - LIKE CONFIGURATION CHAIN JTAG - LIKE CONFIGURATION CHAIN
TEST BUS
Fig. 5.8 Architectures of thea8051-based andbof the LEON-based ISIF
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power-optimized 8051-compliant core we presented in [16,17]. A prototype chip has been realized in 0.35lm BCD technology.
The architecture in Fig.5.8a with a configuration of 32-kbit PROM and two 4-kbit SRAM memories and an 8-bit 8051 core with timer/counter, UART and SPI has an overall area of roughly 20 mm2and works at 20 MHz clock frequency. The ADCs are sized for 10 bits and 100 kS/s max sample rate. The second ISIF gen-eration targets more powerful sensor conditioning systems; it is based on a 32 bit SPARCV8 LEON2 CPU core and is more suited for fast sensor conditioning prototyping, or for applications requiring computation-intensive signal processing but with less bounded limits in terms of chip size and cost. Still realized in 0.35lm BCD technology, this embedded platform (Fig.5.8b) has an area of roughly 70 mm2 and enhances the first generation in Fig.5.8a with: four multi-stage configurable analog (instrumentation amp?filter) acquisition channels; four 12-bit SAR ADCs (max. 150 kS/s) and two 16-bit sigma-delta ADCs (max. 15 kS/s); six high-precision 12-bit and six high-speed 10-bit on chip DACs; a 32 bit 20 MHz SPARC V8 fixed-point core (LEON2); on-chip 32 kbytes EEPROM and 32 kbytes RAM; UART/SPI interface plus 2 timer peripherals and 16-bit GPIO. For the target sensors of this work the 8051-based ISIF embedded device is enough and ensures lower cost and size vs. the second architecture chip. Other mixed-signal platforms for sensor interfacing are available on the market, such as the Actel Fusion (AFS600) based on an ARM7 core and a single 12-bit ADC [18] or the Cypress PSOC CY8C featuring 4 ADCs and 4 DACs configurable from 6 to 14 bits and based on 8-bit CPU. With respect to the above COTS platforms the proposed ISIF device is preferable in the 8051-based version when the application is more ded-icated to the conditioning of sensors with limited size and cost budgets, while the LEON[19]-based version is preferable if high-precision ADCs or a powerful CPU are required. From a SW and algorithmic point of view, the development flow of an application on the ISIF platform is integrated with a system-level Simulink/Matlab flow. The starting point is the realization of a Matlab/Simulink model of the whole system, which is made of a set of functional blocks allowing co-simulation of the sensor model with the analog/digital conditioning circuitry. To this aim to each sub-block in Fig.5.8 a simulating model of the relevant circuitry is associated (detailing input–output transfer characteristic plus main error sources such as saturation, offset, noise, temperature dependence, frequency response). Using such configurable models at an early stage of the design it is possible to run a number of simulations for identifying the critical parameters for the overall system perfor-mance, and hence for correctly sizing the sensor signal processing circuit. A system exploration phase, based on simulations, design iterations and functional blocks refinements leads to a first partitioning of the system in analog and SW-pro-grammable digital building blocks. After architecture definition and HW/SW partitioning in the Matlab/Simulink environment, each block is modeled with the most appropriate description language and EDA tools or proper pre-designed IPs to be reused are selected, configured and assembled. Conventional flows are used for the lower level design phases (VHDL-based for digital HW, VHDL-AMS and Spice for analog circuitry and C/C ++ for SW routines). The top-down 5 IEEE 1451 Sensor Interfacing and Data Fusion in Embedded Systems 69
platform-based design flow ends up with the prototyping phase, through which the whole system can be tested under practical operating conditions. This methodology enables a rapid managing also of complex designs thanks to high reuse of concepts, architectures, and IPs among different projects.
As proved inSect. 5.4data fusion algorithms are very important for measuring H2concentration both in explosion warning systems (targeting with the TGS6812 sensor a dynamic range of several thousands of ppm with a measuring resolution of 100 ppm) and in H2leak detection systems for early warning, targeting with the TGS821 sensor a dynamic range up to 1,000 ppm, but with a fine grained reso-lution. However, it must be noted that the data fusion algorithm, especially the one for TGS821, is computationally complex. Beyond simple additions, subtractions and products, some exponential, logarithm and division operations must be per-formed to calculate the formulas described in Fig.5.5and Eq.5.1. The use of a DSP with Floating Point Unit is required, but this device is expensive compared to a traditional microcontroller and it is not suited for automotive applications, which are intended for a high-volume market. A solution relies on the use of a tabulated form of the needed non linear analog functions, based on pre-calculated Look-Up Tables (LUT) in the digital domain. Naturally, it is necessary to find a trade-off between the number of levels of the tabulated functions and the related memory cost. A coarse function approximation can lead to unacceptable measuring errors;
on the contrary, an approximation with a large number of levels and bits for their encoding can lead to a memory resource requirement too high for the limited budgets of embedded automotive HW. When choosing the LUT-based approach it is necessary to use a processing platform, such as the ISIF, with a PROM that contains the entire array describing the tabulated functions. When sizing the HW platform, first of all the number of ADC’s bits has to be defined. For the H2data fusion algorithm extensive simulations in the Matlab environment have been carried out trying to find the lower number of ADC data size and LUT levels that ensure at system level a quantization error below a ‘quality target’ of 10 ppm for leak detection in the range 0–1,000 ppm and below 100 ppm for explosivity warning in a wider measuring range up to 10,000 ppm. As a result of this design exploration activity, a 10-bit ADC was selected. It has to be noted that from our analysis for humidity and for temperature sensors an 8-bit converter would be sufficient. Therefore, the SAR-type 10-bit ADC of the ISIF platform can be used to acquire the required signals: since the bandwidths of the sensors are in the order of Hz and the sampling rate of the ADC is up to 100 kS/s, all sensor inputs can be multiplexed on the same ADC. To reduce glitch noise when switching between different inputs and to reduce quantization noise (thus having an effective number of bits equal to the nominal 10 bits), the digital conversion can be performed at a higher frequency w.r.t. the required Nyquist-rate and then the digital signal can be cleaned by decimating the samples. This way the resolution obtained using the SAR ADC of the ISIF platform is 2 ppm for TGS821 acquisitions and about 40 ppm for TGS6812 acquisitions.
After sizing the ADC the next choice to be made is related to the size of the tables that will describe the various non-linear functions used for data fusion.
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As example, for the TGS821 the functions in Fig.5.5 have to be tabulated.
Hereafter we report, for each formula, the criteria for sizing the corresponding table, emerged after extensive simulations in the Matlab environment targeting an overall quantization error below 10 ppm. The table that represents the CH4 sen-sitivity function is sufficiently informative if it is implemented with 256 lines of input, divided in the range of concentration of CH4 from 0 to 4,000 ppm, with outputs represented over 8 bits, for a total memory usage of 256 bytes. In order to get a satisfactory approximation of the temperature and humidity sensitivity functions it is necessary a table with 256 entries, where outputs have an 8-bit representation. This way the memory requirement amounts to 256 bytes for each function. The H2 sensitivity function can be calculated in tabular form, using a table with 2,048 input lines and outputs with 8-bit precision. This table requires 2 kbytes of memory. Finally the function that extracts the hydrogen measure from the read output voltage requires a table with 256 entries encoded on 12 bits. The low-cost implementation of the sensor fusion compensation for the TGS6812 device is easier since its dependence on temperature and humidity is negligible and the correlation with methane measurement is based on a linear law. Following the above considerations, the fusion technique for both H2 sensors, TGS8612 and TGS821, can be implemented on a mixed-signal embedded device, such as the 8051-based ISIF platform. Indeed, the required HW resources after the LUT-based strategy and bit sizing reported above are the following: 10-bit ADC with 4 multiplexed channels (one for the hydrogen sensor, TGS6812 or TGS821 depending on the target dynamic range, while the others are for methane com-pensation and in case of the TGS821 for temperature and humidity comcom-pensation);
on-chip memory of roughly 3 kbytes for LUT-based implementation of complex processing functions; 8-bit CPU of few MIPS which implements only digital samples decimation and signal control tasks at low repetition frequencies (the sensors have bandwidth of few Hz); IEEE 1451.2 UART serial interface towards a NCAP host controller. Figure5.9 shows the results obtained imple-menting data fusion for TGS821 on the ISIF platform. Both simulated data of the overall Simulink model and experimental data (different H2concentration points) are illustrated. From Fig.5.9 it can be noted the effect of the representation of values on a limited number of bits and of the LUT-based realization of non-linear equations. The use of LUTs and of a fixed point arithmetic allows the algorithm
Fig. 5.9 TGS821: LUT-based implementation of data fusion algorithm
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implementation in the low-complexity 8051-based ISIF device, instead of using a floating point DSP, and the introduced error with respect to the ideal response curve amounts to tens of ppm. Similar simulation and experimental analysis have been repeated after implementing data fusion for TGS6812 on the ISIF platform.
In this case the maximum error amounts to few hundreds of ppm in a range up to 10,000 ppm.
5.6 Conclusions
The design of an IEEE 1451-compliant embedded system for sensor network interfacing and processing is presented. The achieved results on the case study of gas leak detection for H2-based vehicles prove that intelligent sensor interface IC can be designed integrating on-chip the mixed-signal processing chain plus data fusion and communication digital resources. Beside the detailed design of the smart sensing module (IEEE 1451.2 compliant) the whole monitoring system architecture is discussed, including network capable application processors (NCAP) for both wired (CAN in-vehicle network) and wireless (Wi-Fi network-ing) scenarios. This work is supported by the projectsFiliera H2(Tuscany region) andPollux(EU).
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