• Aucun résultat trouvé

Post-processing

Dans le document Lecture Notes in Electrical Engineering (Page 105-109)

A SystemC Platform for NoC Analysis

7.5 Post-processing

In the following the post-processing data generated by the tool will be described.

Intermediate files that can be generated in each simulation are *.logfiles and they collect all the events that occur during the simulation.

Since every node connected to the network is source and sink of messages, ip_*_source.logandip_*_sink.log files collect events of all the messages gener-ated and consumed by the nodes, respectively. Data are structured in records of one line each; the fields of the record collect the identifier of the message, the time instant of its production or consumption and its destination and length in terms of number of packets. The filename identifies the node.

The write operation on links, operated by the routers, are logged inlink_*.log file. Each record contains the flit identifier, the time instant of the write event and a value of the energy consumption of the transmission of that flit on the link. The filename identifies the link.

The files namedrouter_*_stax.log collects events of arrival and departure of flits in the specified router; the fields of the records are the flit identifier, the time instant of the event, the destination node of the flit, a flag indicating the direction of the event.

The level of utilization of the buffer of each port of the router is stored in the filesrouter_*_buffer_ port.log. Each record contains the buffer identifier, the time instant of the event and the level of occupancy of the buffer normalized to its capacity.

Therouter_*_routing.logfiles collect information about routed packet, namely which packets have been routed toward which port of the router in a certain instant. The files router_*_demux_port*.log, router_*_switch.log and router_*_mux_ port*.loghave the traces of the contentions of the resources in the routers between input port and input buffer, at crossbar and between output buffer and output port, respectively. They store the identifier of the packet that must advance, the resource contended, the result of the contention and a time stamp.

The data stored in the .log files are elaborated in the post-processing phase, allowing an analysis of the NoC performances through synthetic parameters.

7 NOCEXplore 101

If only the statistical analysis is performed, only the fileresult.netis generated, which holds global indexes on communication, energetic and activities performances.

The file contains the mean, maximum, minimum and standard deviation of the delays and the throughput of the messages delivered at steady state condition on the NoC.

Based on power consumed by routers in each state, an estimation of power consumption is done and it is normalized to the maximum power consumption if no power management policy is adopted.

Some activities are collected during simulation: the number of packet routings, the number of flit that have crossed a router, the number of shift in buffer if the structure is considered as shift register and an estimate of the total number of commutation in the links.

The probabilistic analysis elaborates the communication performances, that is latency and throughput, for each couple of nodes connected to the network; the analysis generates two groups of file: the former performs some statical indexes for each flow of traffic and the latter shows the distribution of the delay of the traffic flow.

The six files with namematrix_*_data.elabare tables and the element on the line ‘‘i’’ and column ‘‘j’’ refers to the couple of nodes identified as ‘‘ith’’ node source and ‘‘jth’’ sink node. The data stored are: mean and standard deviation of latency, throughput, number of messages, packets and flit delivered. Each of these table has an associated colour-plot for an immediate and visual trend of com-munication performances for each flow of messages.

Data files with the name prob_source*_sink*.elab contain the distribution of the latencies of the messages composing the traffic flow considered at steady state condition. Each of the 200 records defines the probability ‘‘p’’ of message having delay ‘‘d’’. Each of these function has an associated plot.

The most detailed analysis generates many postprocessing files containing data able to describe the evolution of some parameter during the simulation. Each one of these data file has an associated plot.

The filesutil_router*_inport*.elabandutil_router*_outport*.elabcontain the temporal evolution of the level of occupancy of flit in a specified router in a specified input port or output port, respectively. The files with name util_router*_allport.elabcontain the same parameter, but data are referred to flit in all the buffers in the router.

The other parameters monitored refer to the activities related to statistical analysis. The dynamics of the events of the crossings operated by the switch, the routings decided by the routing module and the writings in link are elaborated with a moving average having windows 10 clock cycles wide. The file containing these data are:switch_ma_*.elab, routing_ma_*.elabandlink_ma_*.elab,respectively;

the substring ‘‘_ma_’’ in the filenames stands for ‘‘moving average’’.

These data are saved in text and graphics mode and in three different time intervals: transient window comprises the first 800 clock cycles; the steady state interval is 800 clock cycles wide and it is located in the middle of the simulation;

102 S. Gigli and M. Conti

the last windows includes all events occurring from the begin to the end of the simulation.

Further elaborations of simulation data stored in the .log files can be easily added.

7.6 Conclusions

NOCEXplore, the Network-on-Chip simulator presented in this chapter, allows the designer to compare the communication and power performances of many Network-on-Chip configurations in different traffic conditions. Furthermore, it allows the investigation on possible bottlenecks. Configuration space is easily upgradeable and postprocessing is customizable. A huge set of network topologies with deep level of investigation and comparison is possible and, at the same time, simulations are performed in a reasonable CPU time. Existing tools do not perform at the same time cycle level analysis and huge design space exploration.

On the other hand, power estimation is technology independent and power models must be entirely provided by users.

This platform will be improved by adding following features:

• new topologies, routing algorithms and traffic scenario will be added;

• accuracy of the estimation of power and performance will be given;

• network hierarchical topologies and mixed bus-NoC architectures will be considered;

• new TLM modules will speed-up simulations time;

• a database will be developed for easy and fast managing and performance consulting of previously simulated networks.

References

1. de Micheli G, Benini L (2002) Networks on chip: a new paradigm for systems on chip design.

In: DATE ‘02: Proceedings of the conference on design, automation and test in Europe. IEEE Computer Society, Washington, p 418

2. Kornaros G (2010) Multi-core embedded systems. Taylor & Francis, Boca Raton

3. Bononi L, Concer N (2006) Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh. In: Proceedings of design, automation and test in Europe (DATE), March

4. Dolter JW, Ramanathan P, Shin KG (1991) Performance analysis of virtual cut-through switching in HARTS: a hexagonal mesh multicomputer. IEEE Trans Multicomput 40(6):669–680

5. Zhao Y-J, Yue Z-H, Wu JP (2008) Research on next-generation scalable routers implemented with H-torus topology. J Comput Sci Technol 23(4):684

6. Guerrier P, Greiner A (2000) A generic architecture for on-chip packet switched interconnections. In: Proceedings of DATE. ACM Press, pp 250–256

7 NOCEXplore 103

7. Kariniemi H, Nurmi J (2003) New adaptive routing algorithm for extended generalized fat trees on-chip. In: Proceedings of the international symposium on system-on-chip, Tampere, Finland, pp 113–188

8. Ohring SR, Ibel M, Das SK, Kumar M (1995) On generalized fat trees. In: Proceedings on 9th international parallel processing symposium

9. Moussa H, Muller O, Baghdadi A, Jezequel M (2007) Butterfly and benes-based on-chip communication networks for multiprocessor turbo decoding. In: Design automation and test in Europe conference

10. Bolotin E, Cidon I, Ginosar R, Kolodny A (2004) QNoC: QoS architecture and design process for network on chip. J Syst Arch Spec Issue Netw Chip 50:105–128

11. Soteriou V, Peh L-S (2004) Design-space exploration for power-aware on/off interconnection networks. In: Proceedings of the 22nd international conference on computer design (ICCD) 12. Shang L, Peh L-S, Jha NK (2002) Power-efficient interconnection networks: dynamic voltage

scaling with links. Comput Arch Lett 1(2):1–4

13. Bhat S (2005) Energy models for network on chip components. Ph.D. dissertation, Technische universiteit Eindhoven

14. Laffely A, Liang J, Jain P, Weng N, Burleson W, Tessier R (2001) Adaptive system on a chip (aSoC) for lowpower signal processing. In: Thirty-fifth asilomar conference on signals, systems, and computers, November

15. Liang J, Swaminathan S, Tessier R (2000) aSOC: a scalable, single-chip communications architecture. In: IEEE international conference on parallel architectures and compilation techniques, October, pp 524–529

16. Dally WJ (1990) Virtual-channel flow control. In: Proceedings of the 17th annual international symposium on computer architecture (ISCA), Seattle, Washington, May, pp 60–68

17. Kermani P, Kleinrock L (1979) Virtual cut-through: a new computer communication switching technique. Comput Netw 3:267–286

18. Dally WJ, Seitz CL (1986) The torus routing chip. J Parallel Distrib Comput 1(3):187–196 19. Peh L-S, Dally WJ (2000) Flit-reservation flow control. In: Proceedings of the 6th international symposium on high-performance computer architecture (HPCA), January, pp 73–84

20. Dally W, Seitz C (1987) Deadlock-free message routing in multiprocessor interconnection networks. IEEE Trans Comput C-36(5):547–553

21. Glass C, Ni L (1994) The turn model for adaptive routing. J ACM 5:874–902

22. Duato J (1995) A necessary and sufficient condition for deadlock-free adaptive routing in wormhole networks. IEEE Trans Parallel Distrib Process 6(10):1055–1067

23. Duato J (1996) A necessary and sufficient condition for deadlock-free routing in cut-through and store-and-forward networks. IEEE Trans Parallel Distrib Process 7:841–854

24. Gigli S, Conti M (2009) A SystemC platform for Network-on-Chip performance/power evaluation and comparison. In: Proceedings of the IEEE seventh international workshop on intelligent solutions in embedded systems WISES09, pp 63–69, Ancona, Italy, June 25–26

104 S. Gigli and M. Conti

Chapter 8

Coverage-Driven Verification of HDL

Dans le document Lecture Notes in Electrical Engineering (Page 105-109)