Logic Circuits
2.3 Sequential Logic
The output of sequential logic refl ects both the inputs and the previous state of the circuit. That is, it remembers the past and incorporates history into the present. A counter whose output is currently 101, for instance, remembers that state to know the next value must be 110.
Sequential circuits are always managed by one or more clocks. A clock is a square wave (or at least one that’s squarish) that repeats at a fi xed frequency. Every sequential circuit is idle until the clock transitions; then, for a moment, everything changes. Counters count. Timers tick.
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UARTs squirt a serial bit. The clock sequences a series of changes; the circuit goes idle after clock changes to allow signals to settle out.
The clock in a computer ensures that every operation has time to complete correctly. It takes time to access memory, for example. A 50 nsec RAM needs 50 nsec to retrieve data after being instructed as to which location to access. The system clock paces operations so the data has time to appear.
Just as gates are the basic units of combinatorial circuits, fl ip-fl ops form all sequential logic. A fl ip-fl op (aka a “fl op” or “bistable”) changes its output based on one or more inputs, after the supplied clock transitions. Databooks show a veritable zoo of varieties. The simplest is the set-reset fl op (SR for short), which looks like Figure 2.1.
1 A
B
2
Figure 2.1: SR fl ip-fl op.
To understand how this works, pretend input A is a zero. Leave B open. It’s pulled to a one by the resistor. With A low, NAND gate 1 must go to a one, supplying a one to the input gate 2, which therefore, since B is high, must go low. Remove input A and gate 2 still drives a zero into gate 1, keeping output 1 high. The fl op has remembered that A was low for a while. Now momentarily drive B low. Like a cat chasing its tail, the pattern reverses: output 1 goes high and 2 low.
What happens if we drive A and B low and release them at the same time? No one knows.
Don’t do that.
Flip fl ops are latches, devices that store information. A RAM is essentially an array of many latches.
Possibly the most common of all sequential components is the D fl ip-fl op. As Figure 2.2 shows, it has two inputs and one output. The value at the D input is transferred to the Q output when clock transitions. Change the D input and nothing happens till clock comes again.
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CLK D
Q
CLK D Q
Figure 2.2: Note that the output of the D fl ip-fl op changes only on the leading edge of clock.
(Some versions also have set and clear inputs that drive Q to a high or low regardless of the clock. It’s not unusual to see a Qoutput as well, which is the inversion of Q.)
Clearly the D fl op is a latch (also known as a register). String eight of these together, tied to one common clock, and you’ve created a byte-wide latch, a parallel output port.
Another common, though often misunderstood, synchronous device is the JK fl ip-fl op, named for its inventor (John Kardash). Instead of a single data input (D on the D fl ip-fl op), there are two, named J and K. Like the D, nothing happens unless the clock transitions.
But when the clock changes, if J is held low, then the Q output goes to a zero (it follows J ). If J is one and K zero, Q also follows J, going to a one.
But if both J and K are one, then the output toggles—it alternates between zero and one every time a clock comes along.
The JK fl ip-fl op can form all sorts of circuits, like the following counter:
CLK CLK
K Q
J Q
Q0
Q0 Q1 Q2
Q1 Q2
K Q
J Q
K Q
J Q
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Every clock transition causes the three outputs to change state, counting through the binary numbers. Notice how the clock paces the circuit’s operation; it keeps things happening at the rate the designer desires.
Counters are everywhere in computer systems; the program counter sequences fetches from memory. Timer peripherals and real-time clocks are counters.
The example above is a ripple counter, so called because a binary pattern ripples through each fl ip-fl op. That’s relatively slow. Worse, after the clock transitions it takes some time for the count to stabilize; there’s a short time when the data hasn’t settled. Synchronous counters are more complex but switch rapidly, with virtually no settle time (Figure 2.3).
Figure 2.3: A 3-bit synchronous counter.
CLK
Cascading JK fl ip-fl ops in a different manner creates a shift register. The input bits march (shift) through each stage of the register as the clock operates (Figure 2.4).
Figure 2.4: A 3-bit shift register.
CLK
Putting a lot of what we’ve covered together, let’s build a simplifi ed UART and driver for an RS-232 device (see Figure 2.5). This is the output part of the system only; considerably more logic is needed to receive serial data, and this drawing doesn’t show the start and stop bits. But it shows the use of a counter, a shift register, and discrete parts.
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RS-232 data is slow by any standard. Normal microprocessor clocks are far too fast for, say, 9600 baud operation. The leftmost chip is an eight-stage counter. It divides the input fre-quency by 256. So a 2.5 MHz clock, often found in slower embedded systems, divided as shown, provides 9600 Hz to the shift register.The register is one that can be parallel-loaded; when the computer asserts the LOAD signal, the CPU’s data bus is preset into the 8 stage shift register IC (middle of the drawing). The clock makes this 8-bit parallel word, loaded into the shift register, march out to the QH output, one bit at a time. A simple transistor amplifi er translates the logic’s 5 volt levels to 12 volts for the RS-232 device.
Figure 2.5: A simplifi ed UART.
S0
Modern embedded systems do use all these sorts of components. However, most designers use integrated circuits that embody complex functions instead of designing with lots of gates and fl ops. A typical IC might be an 8-bit synchronous counter or a 4-bit arithmetic-logic unit (that does addition, subtraction, shifting, and more).
Yet you’ll see gates and fl ops used as “glue” logic, parts needed to interface big complex ICs together.
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