Why Talk About the von Neumann Model?
3.3.3 Processor Input/Output (I/O)
3.3.3.2 Processor Serial I/O Example 1:
An Integrated Universal Asynchronous Receiver-Transmitter
The UART is an example of a full-duplex serial interface that can be integrated into the master processor and that does asynchronous serial transmission. As mentioned earlier, the UART can exist in many variations and under many names; however, they are all based on the same design: the original 8251 UART controller implemented in older PCs. A UART (or something like it) must exist on both sides of the communication channel, in the I/O device as well as on the embedded board, in order for this communication scheme to work.
In this example, we look at the MPC860 internal UART scheme, since it has more than one way to implement a UART. The MPC860 allows for two methods to confi gure a UART, either using a serial communication controller (SCC) or a serial management controller (SMC). Both of these controllers reside in the PowerPC’s Communication Processor
Module (shown in Figure 3.57) and can be confi gured to support a variety of communication schemes, such as Ethernet, HDLC, and the like for the SCC and transparent, GCI, and so on
Note: Different architectures that integrate a UART or other types of serial interfaces can have varying names for the same type of interface, such as the MPC860, which has serial management controller (SMC) UARTs, for example. Review the relevant documentation to understand the specifi cs.
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for SMCs. In this example, however, we are only examining both being confi gured and func-tioning as a UART.
MPC860 SCC in UART Mode
As introduced at the start of this section, in an asynchronous transfer, the data being transmit-ted can be stored and modifi ed within a serial interface’s transmission buffer. With the SCCs on the MPC860, there are two UART fi rst-in/fi rst-out (FIFO) buffers, one for receiving data for the processor and one for transmitting data to external I/O (see Figures 3.58a and b). Both buffers are typically allocated space in main memory.
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Time Slot Assigner Serial Interface SCC1 SCC2 SCC3 SCC4 SMC1 SMC2 I2C
2
Figure 3.57: MPC860 UARTs.[3.44]
Copyright of Freescale Semiconductor, Inc., 2004. Used by permission.
Control Registers
Figure 3.58a: SCC in receive mode.[3.45]
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As shown in Figures 3.58a and b, along with the reception and transmission buffers there are control registers to defi ne the baud rate, the number of bits per character, the parity, and the length of the stop bit, among other things. As shown in Figures 3.58a and b as well as 3.59, there are fi ve pins, extending out from the PowerPC chip, that the SCC is connected to for data transmission and reception: transmit (TxD), receive (RxD), carrier detect (CDx), collision on the transceiver (CTSx), and request-to-send (RTS). The way these pins work together is described in the next few paragraphs.U-Bus
Delimiter Shifter Shifter Delimiter Encoder
Figure 3.58b: SCC in transmit mode.[3.45]
SCC Pin Summary
PA[15] / RXD1
* TXDx - transmit pins
* RTSx - request-to-send pins
* RXDx - receive pins
* CDx - carrier detect pins
* CTSx - clear-to-send pins PA[14] / TXD1
PC[10] / CD1*/TGATE 1 PC[11] / CTS1*
PC[5] / CTS4* / SDACK1 / L1TSYNCA PC[7] / CTS3* / SDACK2 / L1TSYNCB PC[6] / CD3* / L1RSYNCB
PB[18] / RTS2* / L1ST1 or PC[14] / RTS2* / L1ST2 / DREQ1 PC[8] / CD2* / TGATE2
PB[19] / RTS1*/L1ST1 or PC[15]/RTS1*/L1ST1 / DREQ0
Figure 3.59: SCC pinouts.[3.46]
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In either receive or transmit modes, the internal SCC clock is activated. In asynchronous transfers, every UART has its own internal clock that, though unsynchronized with the
clock in the UART of the external I/O device, is set at the same baud rate as that of the UART it is in communication with. The carrier detect (CDx) is then asserted to allow the SCC to receive data, or the collision on the transceiver (CTSx) is asserted to allow the SCC to transmit data.
As mentioned, data is encapsulated into frames in asynchronous serial transmissions. When transmitting data, the SDMA transfers the data to the transmit FIFO and the request-to-send pin asserts (because it is a transmit control pin and asserts when data is loaded into the trans-mit FIFO). The data is then transferred (in parallel) to the shifter. The shifter shifts the data (in serial) into the delimiter, which appends the framing bits (i.e., start bits, stop bits, and so on). The frame is then sent to the encoder for encoding before transmission. In the case of an SCC receiving data, the framed data is then decoded by the decoder and sent to the delimiter to strip the received frame of nondata bits, such as start bit, stop bit(s), and so on. The data is then shifted serially into the shifter, which transfers (in parallel) the received data into the receive data FIFO. Finally, the SDMA transfers the received data to another buffer for contin-ued processing by the processor.
MPC860 SMC in UART Mode
As shown in Figure 3.60a, the internal design of the SMC differs greatly from the internal design of the SCC (shown in Figures 3.58a and b), and in fact has fewer capabilities than an SCC. An SMC has no encoder, decoder, delimiter, or receive/transmit FIFO buffers.
It uses registers instead. As shown in Figure 3.60b, there are only three pins that an SMC is connected to: a transmit pin (SMTXDx), a receive pin (SMRXDx), and sync signal pin (SMSYN). The sync pin is used in transparent transmissions to control receive and transmit operations.
Control Registers U-Bus
Peripheral Bus
Control Receive Unit
Data Register
Transmit Data Register
RxD TxD
SYNC Internal Clocks
Clock Generator MUX Baud Rate Generator(s) CLKx
SDMA
Shifter Shifter
Figure 3.60a: SMC.[3.47]
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Data is received via the receive pin into the receive shifter, and the SDMA then transfers the received data from the receive register. Data to be transmitted is stored in the transmit register and then moved into the shifter for transmission over the transmit pin. Note that the SMC does not provide the framing and stripping of control bits (i.e., start bit, stop bit[s], and so on) that the SCC provides.Processor Serial I/O Example: An Integrated Serial Peripheral Interface (SPI)
The SPI is an example of a full-duplex serial interface that can be integrated into the master processor and that does synchronous serial transmission. Like the UART, an SPI needs to exist on both sides of the communication channel (in the I/O device as well as on the embed-ded board) in order for this communication scheme to work. In this example, we examine the MPC860 internal SPI, which resides in the PowerPC’s Communication Processor Module (shown in Figure 3.61).
*SMTXDx - transmit pins
*SMRXDx - receive pins PB[24]/SMRXD1
*SMSYNx - synch signal pins for transparent
Figure 3.60b: SMC pins.[3.47]
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SCC1 SCC2 SCC3 SCC4 SMC1 SMC2 SPI1 I2C 2
Figure 3.61: MPC860 SPI.[3.48]
Copyright of Freescale Semiconductor, Inc., 2004. Used by permission.
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In a synchronous serial communication scheme, both devices are synchronized by the same clock signal generated by one of the communicating devices. In such a case, a mas-ter-slave relationship develops in which the master generates the clock signal which it and the slave device, adheres to. It is this relationship that is the basis of the four pins that the MPC860 SPI is connected to (as shown in Figure 3.62b): the master out/slave in or transmit (SPIMOSI), master in/slave out or receive (SPIMISO), clock (SPICLK), and slave select (SPISEL).
Control Registers U-Bus
SDMA
Peripheral Bus Receive Reg Transmit Reg
SPI Mode Reg
Shift_Register TXD
BRGCLK SPI BRG Pins Interface
IN CLK RXD Counter
3 1
2
SPISEL* SPIMOSI SPIMISO SPICLK
Figure 3.62a: SPI.[3.49]
* SPIMOSI - master out, slave in pin
* SPIMOSI - master in, slave out pin
* SPICLK - SPI clock pin
PB[30]/SPICLK
PB[31]/SPISEL*/REJECT1*
PB[28]/SPIMISO/BRGO4 PB[29]/SPIMOSI
Clock SPIMOSI SPIMISO SPISEL*
* SPISEL - SPI slave select pin, used when 860 SPI is in slave mode
Figure 3.62b: SPI pins.[3.49]
When the SPI operates in a master mode, it generates the clock signals, while in slave mode, it receives clock signals as input. SPIMOSI in master mode is an output pin, SPMISO in master mode is an input pin, SPICLK supplies an output clock signal in master mode that
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synchronizes the shifting of received data over the SPIMISO pin or shifts out transmitted data over SPIMOSI. In slave mode, SPIMOSI is an input pin, SPIMISO is an output pin, and SPICLK receives a clock signal from the master synchronizing the shifting of data over the transmit and receive pins. The SPISEL is also relevant in slave mode because it enables input into the slave.The way these pins work together, along with the internal components of the SPI, is shown in Figure 3.62a. Essentially, data is received or transmitted via one shift register. If data is received, it is then moved into a receive register. The SDMA then transfers the data into a receive buffer that usually resides in main memory. In the case of a data transmission, the SDMA moves the data to be transmitted from the transfer buffer in main memory to the trans-mit register. SPI transmission and reception occurs simultaneously; as data is received into the shift register, it shifts out data that needs to be transmitted.
3.3.3.2 Parallel I/O
I/O components that transmit data in parallel allow data to be transferred in multiple bits simultaneously. Just as with serial I/O, parallel I/O hardware is also typically made up of some combination of six main logical units, as introduced at the start of this chapter, except that the port is a parallel port and the communication interface is a parallel interface.
Parallel interfaces manage the parallel data transmission and reception between the master CPU and either the I/O device or its controller. They are responsible for decoding data bits received over the pins of the parallel port, transmitted from the I/O device, and receiving data being transmitted from the master CPU, and then encoding these data bits onto the parallel port pins.
They include reception and transmission buffers to store and manipulate the data they are responsible for transmitting either to the master CPU or an I/O device. Parallel data transmis-sion and reception schemes, like serial I/O transmistransmis-sion, generally differ in terms of the direc-tion in which data can be transmitted and received as well as the actual process of how the data bits are transmitted (and thus received) within the data stream. In the case of direction of transmission, as with serial I/O, parallel I/O uses simplex, half-duplex, or full-duplex modes.
Again, like serial I/O, parallel I/O can be transmitted asynchronously or synchronously.
Unlike serial I/O, parallel I/O does have a greater capacity to transmit data, because multiple bits can be transmitted or received simultaneously. Examples of I/O devices that transfer and receive data in parallel include IEEE1284 controllers (for printer/display I/O devices), CRT ports, and SCSI (for storage I/O devices).