Embedded Board Buses and I/O
4.6 Bus Arbitration and Timing
4.6.2 PCI (Peripheral Component Interconnect) Bus Example: Expandable
The latest PCI specifi cation at the time of writing, PCI Local Bus Specifi cation Revision 2.1, defi nes requirements (mechanical, electrical, timing, protocols, etc.) of a PCI bus
implementation. PCI is a synchronous bus, meaning that it synchronizes communication using a clock. The latest standard defi nes a PCI bus design with at least a 33 MHz clock (up to 66 MHz) and a bus width of at least 32 bits (up to 64 bits), giving a possible minimum
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throughput of approximately 132 Mbytes/sec ((33 MHz * 32 bits) / 8)—and up to 528 Mbytes/
sec maximum with 64-bit transfers given a 66-MHz clock. PCI runs at either of these clock speeds, regardless of the clock speeds at which the components attached to it are running.
As shown in Figure 4.37, the PCI bus has two connection interfaces: an internal PCI inter-face that connects it to the main board (to bridges, processors, etc.) via EIDE channels, and
Figure 4.36a: I2C data transfer example.
SDA
Figure 4.36b: I2C complete transfer diagram.
SDA
clock line held low while interrupts are serviced
Figure 4.37: PCI bus.
Signal Name CLK FRAME#
AD[31:0]
C/BE#[3:0] Bus command (address phase) Byte enables (data phases) Address/Data bus (multiplexed) Bus Clock (normally 33MHz; DC okay) Indicates start of a bus cycle
IRDY#
TRDY#
DEVSEL#
RST#
PAR Parity on AD, C/BE#
System Reset Address recognized Ready signal from target Ready signal from master
STOP#
Chip select during initialization transactions Request to stop transaction
ILESD
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the expansion PCI interface, which consists of the slots into which PCI adaptor cards (audio, video, etc.) plug. The expansion interface is what makes PCI an expandable bus; it allows for hardware to be plugged into the bus, and for the entire system to automatically adjust and operate correctly.Under the 32-bit implementation, the PCI bus is made up of 49 lines carrying multiplexed data and address signals (32 pins), as well as other control signals implemented via the remaining 17 pins (see table in Figure 4.37).
Because the PCI bus allows for multiple bus masters (initiators of a bus transaction), it imple-ments a dynamic centralized, parallel arbitration scheme (see Figure 4.38). PCI’s arbitration scheme basically uses the REQ# and GNT# signals to facilitate communication between initi-ators and bus arbitriniti-ators. Every master has its own REQ# and GNT# pin, allowing the arbitra-tor to implement a fair arbitration scheme, as well as determining the next target to be granted the bus while the current initiator is transmitting data.
In general, a PCI transaction is made up of fi ve steps:
1. An initiator makes a bus request by asserting a REQ# signal to the central arbitrator.
2. The central arbitrator does a bus grant to the initiator by asserting GNT# signal.
3. The address phase which begins when the initiator activates the FRAME# signal, and then sets the C/BE[3:0]# signals to defi ne the type of data transfer (memory or I/O read or write). The initiator then transmits the address via the AD[31:0] signals at the next clock edge.
4. After the transmission of the address, the next clock edge starts the one or more data phases (the transmission of data). Data is also transferred via the AD[31:0] signals.
The C/BE[3:0], along with IRDY# and #TRDY signals, indicate if transmitted data is valid.
Figure 4.38: PCI arbitration scheme.
Device 0
busy
request grant grant grant
request request
arb Device
1
Device N
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Figure 4.39a: PCI read example.
CLK Cycle 1 – The bus is idle.
CLK Cycle 2 – The initiator asserts a valid address and places a read com-mand on the C/BE# signals.
** Start of address phase. **
CLK Cycle 3 – The initiator tri-states the address in preparation for the target driving read data. The initiator now drives valid byte enable information on the C/BE# signals. The initiator asserts IRDY# low in-dicating it is ready to capture read data. The target asserts DEVSEL#
low (in this cycle or the next) as an acknowledgment it has positively decoded the address. The target drives TRDY# high indicating it is not yet providing valid read data.
CLK Cycle 4 – The target provides valid data and asserts TRDY# low indi-cating to the initiator that data is valid. IRDY# and TRDY# are both low during this cycle causing a data transfer to take place.
** Start of fi rst data phase occurs, and the initiator captures the data. **
CLK Cycle 5 – The target deasserts TRDY# high indicating it needs more time to prepare the next data transfer.
CLK Cycle 6 – Both IRDY# and TRDY# are low.
** Start of next data phase occurs, and the initiator captures the data pro-vided by the target. **
CLK Cycle 7 – The target provides valid data for the third data phase, but the initiator indicates it is not ready by deasserting IRDY# high.
CLK Cycle 8 – The initiator re-asserts IRDY# low to complete the third data phase. The initiator drives FRAME# high indicating this is the fi nal data phase (master termination).
** Final data phase occurs, the initiator captures the data provided by the target, and terminates. **
CLK Cycle 9 – FRAME#, AD, and C/BE# are tri-stated, as IRDY#, TRDY#, and DEVSEL# are driven inactive high for one cycle prior to being tri-stated.
DATA TRANSFER DATA TRANSFER DATA TRANSFER
Figure 4.39b: PCI write example.
BE#2 BE#3
WAIT WAIT WAIT
DATA TRANSFER DATA TRANSFER DATA TRANSFER
CLK
CLK Cycle 2 – The initiator asserts a valid address and places a write command on the C/BE# signals.
** Start of address phase. **
CLK Cycle 3 – The initiator drives valid write data and byte enable signals. The initiator asserts IRDY# low indicating valid write data is available. The target asserts DEVSEL# low as an acknowledgment it has positively de-coded the address (the target may not assert TRDY# before DEVSEL#).
The target drives TRDY# low indicating it is ready to capture data. Both IRDY# and TRDY# are low.
** First data phase occurs with target capturing write data. **
CLK Cycle 4 – The initiator provides new data and byte enables. Both IRDY#
and TRDY# are low.
** Next data phase occurs with target capturing write data. **
CLK Cycle 5 – The initiator deasserts IRDY# indicating it is not ready to pro-vide the next data. The target deasserts TRDY# indicating it is not ready to capture the next data.
CLK Cycle 6 – The initiator provides the next valid data and asserts IRDY# low.
The initiator drives FRAME# high indicating this is the final data phase (master termination). The target is still not ready and keeps TRDY# high.
CLK Cycle 7 – The target is still not ready and keeps TRDY# high.
CLK Cycle 8 – The target becomes ready and asserts TRDY# low. Both IRDY#
and TRDY# are low.
** Final data phase occurs with target capturing write data. **
CLK Cycle 9 – FRAME#, AD, and C/BE# are tri-stated, as IRDY#, TRDY#, and DEVSEL# are driven inactive high for one cycle prior to being tri-stated.
5. Either the initiator or target can terminate a bus transfer through the deassertion of the
#FRAME signal at the last data phase transmission. The STOP# signal also acts to terminate all bus transactions
Figures 4.39a and b demonstrate how PCI signals are used for transmission of information.
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