Embedded Board Buses and I/O
4.2.5 Parallel I/O Example 3: “Parallel” Output and Graphics I/O
Technically, the models and images that are created, stored, and manipulated in an embedded system are the graphics. There are typically three logical components (engines) of I/O graph-ics on an embedded board, as shown in Figure 4.14:
Geometric Engine Rendering Engine Display Engine Embedded System
Input I/O Device
Output I/O Device
Display Pipeline
Figure 4.14: Graphical design engines.
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The geometric engine, which is responsible for defi ning what an object is. This includes implementing color models, an object’s physical geometry, material and lighting properties, and so on.•
The rendering engine, which is responsible for capturing the description of objects.This includes providing functionality in support of geometric transformations, projec-tions, drawing, mapping, shading, illumination, and so on.
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The raster and display engine, which is responsible for physically displaying the object. It is in this engine that the output I/O hardware comes into play.An embedded system can output graphics via softcopy (video) or hardcopy (on paper) means.
The contents of the display pipeline differ according to whether the output I/O device outputs hard or soft graphics, so the display engine differs accordingly, as shown in Figures 4.15a and b.
Figure 4.15a: Display engine of softcopy (video) graphics example.
CRT
LCD
… Display Engine
Display Pipeline Parallel Display Interface
Controller or
Integrated Master CPU Parallel Interface
Memory (Frame Buffer)
Video Controller
Parallel Port
Figure 4.15b: Display engine of hardcopy graphics example.
… Display Engine
Parallel Display Interface Controller
or
Integrated Master CPU Parallel Interface
Printer Controller
Parallel Port
Display Pipeline
Printer
Scanner
The actual parallel port confi guration differs from standard to standard in terms of the number of signals and the required cable. For example, on Net Silicon’s NETARM50 embedded
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board (see Figure 4.16), the master processor (an ARM7-based architecture) has an integrated IEEE 1284 interface, a confi gurable MIC controller integrated in the master processor, to transmit parallel I/O over four on-board parallel ports.The IEEE 1284 specifi cation defi nes a 40-signal port, but on the NetARM50 board, data and control signals are multiplexed to minimize the master processor’s pin count. Aside from eight data signals DATA[8:1] (D0 – D7), IEEE 1284 control signalsinclude:
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PDIR, which is used for bidirectional modes and defi nes the direction of the external data transceiver. Its state is directly controlled by the BIDIR bit in the IEEE 1284 Control register (0 state, data is driven from the external transceiver toward 1285, the cable, and in the 1 state, data is received from the cable).•
PIO, which is controlled by fi rmware. Its state is directly controlled by the PIO bit in the IEEE 1284 Control register.•
LOOPBACK, which confi gures the port in external loopback mode and can be used to control the mux line in the external FCT646 devices (set to 1, the FCT646 transceivers drive inbound data from the input latch and not the real-time cable interface). Its state is directly controlled by the LOOP bit in the IEEE 1284 Control register. The LOOP strobe signal is responsible for writing outbound data into the inbound latch (complet-ing the loop back path). The LOOP strobe signal is an inverted copy of the STROBE*signal.
Figure 4.16: NETⴙARM50 embedded board parallel I/O.
All NETARM
*MIC Multi Interface Controller
*MIC Port
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STROBE* (nSTROBE), AUTOFD* (nAUTOFEED), INIT* (nINIT), HSELECT* (nSE-LECTIN), *ACK (nACK), BUSY, PE, PSELECT (SELECT), *FAULT (nER-ROR), … 4.2.6 Parallel and Serial I/O Example 4: Networking and Communications—Ethernet One of the most widely implemented LAN protocols is Ethernet, which is primarily based on the IEEE 802.3 family of standards. These standards defi ne the major components of any Ethernet system. Thus, to fully understand an Ethernet system design, you fi rst need to under-stand the IEEE specifi cations. (Remember, this is not a book about Ethernet, and there is a lot more involved than is covered here. This example is about understanding a networking proto-col and then being able to understand the design of a system based on a networking protoproto-col such as Ethernet.)The fi rst step is understanding the main components of an Ethernet system, regardless of whether these components are implemented in hardware or software. This is important since different embedded architectures and boards implement Ethernet components differently. On most platforms, however, Ethernet is implemented almost entirely in hardware.
The hardware components can all be mapped to the physical layer of the OSI model. The fi rmware (software) required to enable Ethernet functionality maps to the lower section of the OSI data-link layer but will not be discussed in this section.
Several Ethernet system models are described in the IEEE 802.3 specifi cation, so let’s look at a few to get a clear understanding of some of the most common Ethernet hardware components.
Ethernet devices are connected to a network via Ethernet cables: thick coax (coaxial), thin coax, twisted-pair, or fi ber optic cables. These cables are commonly referred to by their IEEE names. These names are made up of three components: the data transmission rate, the type of signaling used, and either the cable type or cable length.
Network
Ethernet Data-Link
Application Presentation Session Transport
Physical
Figure 4.17: OSI model.
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For example, a 10Base-T cable is an Ethernet cable that handles a data transmission rate of 10 Mbps (million bits per second), will only carry Ethernet signals (baseband signaling), and is a twisted-pair cable. A 100Base-F cable is an Ethernet cable that handles a data transmis-sion rate of 100 Mbps, supports baseband signaling, and is a fi ber optic cable. Thick or thin coax cables transmit at speeds of 10 Mbps and support baseband signaling but differ in the length of maximum segments cut for these cables (500 meters for thick coax, 200 meters for thin coax). Thus, these thick coax cables are called 10Base-5 (short for 500), and thin coax cables are called 10Base-2 (short for 200).The Ethernet cable must then be connected to the embedded device. The type of cable, along with the board I/O (communication interface, communication port, etc.), determines whether the Ethernet I/O transmission is serial or parallel. The Medium Dependent Interface (MDI) is the network port on the board into which the Ethernet cable plugs. Different MDIs exist for the different types of Ethernet cables. For example, a 10Base-T cable has a RJ-45 jack as the MDI. In the system model of Figure 4.18, the MDI is an integrated part of the transceiver.
Figure 4.18: Ethernet components diagram.
Embedded Device
1 Mbps and 10 Mbps Ethernet System Model
MAU
AUI
Ethernet Interface
MDI PMA PLS MAC/MAC Control
Ethernet Cable
Master or Slave Processor
A transceiver is the physical device that receives and transmits the data bits; in this case it is the Medium Attachment Unit (MAU). The MAU contains not only the MDI but the Physical Medium Attachment (PMA) component as well. It is the PMA which “contains the functions for transmission, reception, and” depending on the transceiver, “collision detection, clock recovery and skew alignment” (p. 25, IEEE 802.3 Spec). Basically, the PMA serializes (breaks down into a bit stream) code groups received for transmission over the transmission medium or deserializes bits received from the transmission medium and converts these bits into code groups.
The transceiver is then connected to an Attachment Unit Interface (AUI), which carries the encoded signals between an MAU and the Ethernet interface in a processor. Specifi cally,
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the AUI is defi ned for up to 10 Mbps Ethernet devices and specifi es the connection between the MAU and the Physical Layer Signaling (PLS) sublayer (signal characteristics, connectors, cable length, etc.).
The Ethernet interface can exist on a master or slave processor and contains the remaining Ethernet hardware and software components. The Physical Layer Signaling (PLS) component monitors the transmission medium and provides a carrier sense signal to the Media Access Control (MAC) component. It is the MAC that initiates the transmission of data, so it checks the carrier signal before initiating a transmission, to avoid contention with other data over the transmission medium.
Let’s start by looking at an embedded board for an example of this type of Ethernet system.
4.2.7 Example 1: Motorola/Freescale MPC823 FADS Board Ethernet