RISC AND CISC

One of the key features used to categorize a microprocessor is whether it supports reduced instruc-tion set computing (RISC—pronounced “risk”) or complex instruction set computing (CISC—pro-nounced “sisk”). The distinction is how complex individual instructions are and how many permutations exist for the same basic instruction. In practical terms, this distinction directly relates to the complexity of a microprocessor’s instruction decoding logic; a more complex instruction set requires more complex decoding logic. Some engineers believe that a microprocessor should exe--Balch.book Page 145 Thursday, May 15, 2003 3:46 PM

Copyright 2003 by The McGraw-Hill Companies, Inc. Click Here for Terms of Use.

146 Advanced Digital Systems

cute simple instructions at a high rate—perhaps one instruction per cycle. Others believe that a mi-croprocessor should execute more complex instructions at a lower rate.

Operand types add complexity to an instruction set when a single general operation such as addi-tion can be invoked with many different addressing modes. Motorola’s CISC 68000 contains a basic addition instruction, among other addition operations, that can be decoded in many different ways according to the specified addressing mode. Table 7.1 shows the format of the basic ADD/ADDA/ ADDX instruction word. ADD is used for operations primarily on data registers. ADDA is used for op-erations primarily on address registers. ADDX is used for special addition operations that incorporate the ALU extended carry bit, X, into the sum. The instruction word references Register1 directly and an effective address (EA) that can represent another register or various types of indirect and indexed addressing modes.

As listed in Table 7.2, the opmode field defines whether the operands are 8-, 16-, or 32-bit quanti-ties and identifies the source and destination operands. In doing so, it also implies certain subclasses of instructions: ADD, ADDA, or ADDX.

The main complexity is introduced by the EAfields as defined in Table 7.3. For those modes that map to multiple functions, additional identifying fields and operands are identified by one or more extension words that follow the instruction word. One of the more complex modes involves using an address register as a base address, adding a displacement to that base to calculate a fetch address, fetching the data at that address, adding another register to the retrieved value, adding another dis-placement, and then using the resulting address to fetch a final operand value. ADD/ADDA/ADDX is TABLE 7.1 68000 ADD/ADDA/ADDX Instruction Word

Bit Position 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Field Opcode = 1101 Register1 Opmode

Effective Address Mode Register2

TABLE 7.268000 ADD/ADDA/ADDX Instruction Opmode Field

Opmode Value Operand Width Definition of Register1 Operation Instruction Mapping

000 8 Dn EA + Dn ⇒ Dn ADD

001 16 Dn EA + Dn ⇒ Dn ADD

010 32 Dn EA + Dn ⇒ Dn ADD

100 8 Dn Dn + EA ⇒ EA ADD/ADDX

101 16 Dn Dn + EA ⇒ EA ADD/ADDX

110 32 Dn Dn + EA ⇒ EA ADD/ADDX

011 16 An EA + An ⇒ An ADDA

111 32 An EA + An ⇒ An ADDA

-Balch.book Page 146 Thursday, May 15, 2003 3:46 PM

Advanced Microprocessor Concepts 147

a powerful instruction that requires significant decode logic behind it. Additionally, when opmode indicates an ADD or ADDX instruction, the two mode values that normally indicate simple register references now map to one of two special ADDX operations.

As can be readily observed, decoding an addition instruction on the 68000 is not as simple as add-ing two registers. For the most complex addressadd-ing modes, multiple registers must be added together to create an address from which another address is fetched that is added with an offset to yield a final address at which the true operand is located. This sounds complicated, and it is. There is really no succinct way to explain the operation of such instructions. The impact of these complex addressing modes on decoding logic is substantial, especially when it is realized that the 68000 contains dozens of instructions, each with its own permutations.

TABLE 7.3 68000 Effective Address Field Definition

Mode Field Definition of Register2 Operand Value Function

000 Data register N Dn Data register value

001 Address register N An Address register value

010 Address register N (An) Indirect address register 011 Address register N (An)+ Indirect with post-increment 100 Address register N –(An) Indirect with pre-decrement 101 Address register N (An + d₁₆,) Indirect with 16-bit displacement

110 Address register N (An + Xn + d₈) Indirect with index register and 8-bit displacement (exten-sion word follows)

(An + Xn + d_16,32) Indirect with index register and 32- or 16-bit displacement (extension words follow)

((An + d_16,32) + Xn + d_16,32) Indirect with displacement to fetch pointer added to index register and displacement (extension words follow) ((An + Xn + d_16,32) + d_16,32) Indirect with displacement and index register to fetch

pointer added to displacement (extension words follow)

111 000 d₁₆ 16-bit direct address (extension word follows)

111 001 d₃₂ 32-bit direct address (extension words follow)

111 100 #data Immediate follows in extension words

111 010 (PC + d₁₆) Indirect with 16-bit displacement

111 011 <multiple> Same as mode=110, but with PC instead of address regis-ters

Shaded modes are invalid when EA is specified as the destination by opmode and change their meaning as follows:

000 Data register N Dn ADDX: Dregister2 + Dregister1 + X ⇒ Dregister1 001 Address register N –(An) ADDX: –(Aregister2) + –(Aregister1) + X ⇒ (Aregister1) -Balch.book Page 147 Thursday, May 15, 2003 3:46 PM

148 Advanced Digital Systems

In contrast to the 68000’s CISC architecture, the MIPS family of microprocessors is one of the commercial pioneers of RISC. MIPS began as a 32-bit architecture with 32-bit instruction words and 32 general-purpose registers. In the 1990s the architecture was extended to 64 bits. MIPS instruction words are classified into three basic types: immediate (I-type), jump (J-type), and register (R-type).

The original MIPS architecture supports four 32-bit addition instructions without any addressing mode permutations: add signed (ADD), add unsigned (ADDU), add signed immediate (ADDI), and add unsigned immediate (ADDIU). These instructions are represented by two types of instruction words, I-type and R-type, as shown in Table 7.4.

The immediate operations specify two registers and a 16-bit immediate operand: R_T = R_S + Im-mediate. The other instructions operate on registers only and allow the programmer to specify three registers: R_D = R_S + R_T. If you want to add data that is in memory, that data must first be loaded into a register. Whereas a single 68000 instruction can fetch a word from memory, increment the associ-ated pointer register, add the word to another register, and then store the result back into memory, a MIPS microprocessor would require separate instructions for each of these steps. This is in keeping with RISC concepts: use more simpler instructions to get the job done.

Instruction decode logic for a typical RISC microprocessor can be much simpler than for a CISC counterpart, because there are fewer instructions to decode and fewer operand complexities to recog-nize and coordinate. Generally speaking, a RISC microprocessor accesses data memory only with dedicated load/store instructions. Data manipulation instructions operate solely on internal registers and immediate operands. Under these circumstances, microprocessor engineers are able to heavily optimize their design in favor of the reduced instruction set that is supported. It turns out that not all instructions in a CISC microprocessor are used with the same frequency. Rather, there is a core set of instructions that are called most of the time, and the rest are used infrequently. Those that are used less often impose a burden on the entire system, because they increase the permutations that the de-code logic must handle in any given clock cycle. By removing the operations that are not frequently used, the microprocessor’s control logic is simplified and can therefore be made to run faster. The re-sult is improved throughput for the most commonly executed operations, which translates directly into greater performance overall.

The fundamental assumption that RISC microprocessors rely on to maintain their throughput is high memory bandwidth. For a RISC microprocessor to match or outperform a CISC microproces-TABLE 7.4 MIPS Addition Instruction Words

I-type bits 31:26 25:21 20:16 15:0

Field Opcode Source Register Target Register Immediate data

ADDI 001000 Rn Rn Data

ADDIU 001001 Rn Rn Data

R-type bits 31:26 25:21 20:16 15:11 10:6 5:0

Field Opcode Source Register Target Register Destination Register Shift Amount Function

ADD 000000 Rn Rn Rn 00000 100000

ADDU 000000 Rn Rn Rn 00000 100001

-Balch.book Page 148 Thursday, May 15, 2003 3:46 PM

Advanced Microprocessor Concepts 149

sor, it must be able to rapidly fetch instructions, because several RISC instructions are necessary to match the capabilities of certain CISC instructions. An older computer architecture with an asyn-chronous memory interface may not be able to provide sufficient instruction bandwidth to make a RISC microprocessor efficient. CISC architectures dominated off-the-shelf microprocessor offerings until low-latency memory subsystems became practical at a reasonable cost. Modern computer ar-chitectures implement very fast memory interfaces that are able to provide a steady stream of in-structions to RISC microprocessors.

One fundamental technique for improving the instruction fetch bandwidth is to design a micro-processor with two memory interfaces—one for instructions and one for data. This is referred to as a Harvard architecture, as compared to a conventional von Neumann architecture in which instruction and data memory are unified. Using a Harvard architecture, instruction fetches are not disrupted by load/store operations. Unfortunately, a Harvard architecture presents numerous system-level prob-lems of how to split program and data memory and how to load programs into memory that cannot be accessed by load/store operations. Most microprocessors that implement a Harvard architecture do so with smaller on-chip memory arrays that can store segments of program and data that are fetched from and written back to a unified memory structure external to the microprocessor chip.

While this may sound so complex as to only be in the realm of serious number-crunchers, the small but powerful 8-bit PIC^TM RISC microcontrollers from Microchip Technology implement a Harvard architecture with mutually exclusive program and data memory structures located on chip. This il-lustrates the point that advanced microprocessor concepts can be applied to any level of performance if a problem needs to be solved.

The RISC concept appears to have won the day in the realm of high-performance computing.

With memory bandwidth not being much of a hindrance, streamlined RISC designs can be made fast and efficient. In embedded computing applications, the victor is less clear. CISC technology is still firmly entrenched in a market where slow memory subsystems are still common and core micropro-cessor throughput is not always a major design issue. What is clear is that engineers and marketers will continue to debate and turn out new products and literature to convince others why their ap-proach is the best available.