Digital Logic
1.13 DERIVED LOGICAL BUILDING BLOCKS
Basic logic gates and flops can be combined to form more complex structures that are treated as building blocks when designing larger digital systems. There are various common functions that an engineer does not want to redesign from scratch each time. Some of the common building blocks are multiplexers, demultiplexers, tri-state buffers, registers, and shift registers. Counters represent an-other building block alluded to in the previous discussion of synchronous logic. A counter is a com-bination of flops and gates that can count either up or down, depending on the implementation.
Multiplexers, sometimes called selectors, are combinatorial elements that function as a multiposi-tion logical switches to select one of many inputs. Figure 1.20 shows a common schematic represen-tation of a multiplexer, often shortened to mux. A mux has an arbitrary number of data inputs, often an even power of two, and a smaller number of selector inputs. According to the binary state of the selector inputs, a specific data input is transferred to the output.
Muxes are useful, because logic circuits often need to choose between multiple data values. A counter, for example, may choose between loading a next count value or loading an arbitrary value from external logic. A possible truth table for a 4-to-1 mux is shown in Table 1.15. Each selector in-put value maps to one, and only one, data inin-put.
A demultiplexer, also called a demux, performs the inverse operation of a mux by transferring a single input to the output that is selected by select inputs. A demux is drawn similarly to a mux, as shown in Fig. 1.21.
TABLE 1.15 Four-to-One Multiplexer Truth Table
S1 S0 Y
0 0 A
0 1 B
1 0 C
1 1 D
A B C D
Y
S1 S0
FIGURE 1.20 Four-to-one multiplexer.
A B C D Din
S1 S0
FIGURE 1.21 One-to-four demultiplexer.
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Digital Logic 29
A possible truth table for a 1-to-4 demux is shown in Table 1.16. Those outputs that are not se-lected are held low. The output that is sese-lected assumes the state of the data input.
A popular use for a demux is as a decoder. The main purpose of a decoder is not so much to trans-fer an input to one of several outputs but simply to assert one output while not asserting those that are not selected. This function has great utility in microprocessor address decoding, which involves selecting one of multiple devices (e.g., a memory chip) at a time for access. The truth table for a 2-to-4 decoder is shown in Table 1.17. The decoder’s outputs are active-low, because most memory and microprocessor peripheral chips use active-low enable signals.
Tri-state buffers are combinatorial elements that can drive three out-put states rather than the standard 0 and 1 states. The third state is off, often referred to as high-impedance, hi-Z, or just Z. Tri-state buffers enable multiple devices to share a common output wire by cooperatively agreeing to have only one device drive the wire at any one time, during which all other devices remain in hi-Z. A tri-state buffer is drawn as shown in Fig. 1.22.
A tri-state buffer passes its D-input to Y-output when enabled.
Otherwise, the output will be turned off as shown in Table 1.18.
Electrically, tri-state behavior allows multiple tri-state buffers to be connected to the same wire without contention. Contention normally results when multiple outputs are connected together be-cause some want to drive high and some low. This creates potentially damaging electrical contention (a short circuit). However, if multiple tri-state buffers are connected, and only one at a time is en-abled, there is no possibility of contention. The main advantage here is that digital buses in comput-TABLE 1.16 One-to-Four Demultiplexer
Truth Table
S1 S0 A B CD
0 0 Din 0 0 0
0 1 0 Din 0 0
1 0 0 0 Din 0
1 1 0 0 0 Din
TABLE 1.17 Two-to-Four Decoder Truth Table
S1 S0 A B CD
0 0 0 1 1 1
0 1 1 0 1 1
1 0 1 1 0 1
1 1 1 1 1 0
EN
D Y
FIGURE 1.22 Tri-state buffer.
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30 Digital Fundamentals
ers can be arbitrarily expanded by adding more devices without the need to add a full set of input or output signals each time a new device is added. In a logical context, a bus is a collection of wires that serve a common purpose. For example, a computer’s data bus might be eight wires that travel to-gether and collectively represent a byte of data. Electrical contention on a bus is often called a bus-fight. Schematically, multiple tri-state buffers might be drawn as shown in Fig. 1.23.
Each tri-state buffer contains its own enable signal, which is usually driven by some type of de-coder. The decoder guarantees that only one tri-state buffer is active at any one time, preventing con-tention on the common wire.
Registers are collections of multiple flops arranged in a group with a common function. They are a common synchronous-logic building block and are commonly found in multiples of 8-bit widths, thereby representing a byte, which is the most common unit of information exchange in digital sys-tems. An 8-bit register provides a common clock and clock enable for all eight internal flops. The clock enable allows external control of when the flops get reloaded with new D-input values and when they retain their current values. It is common to find registers that have a built-in tri-state buffer, allowing them to be placed directly onto a shared bus without the need for an additional tri-state buffer component.
Whereas normal registers simply store values, synchronous elements called shift registers manip-ulate groups of bits. Shift registers exist in all permutations of serial and parallel inputs and outputs.
The role of a shift register is to somehow change the sequence of bits in an array of bits. This in-cludes creating arrays of bits from a single bit at a time (serial input) or distributing an array of bits one bit at a time (serial output). A serial-in, parallel-out shift register can be implemented by chain-ing several flops together as shown in Fig. 1.24.
TABLE 1.18 Tri-state Buffer Truth Table
EN D Y
0 x Z
1 0 0
1 1 1
FIGURE 1.23 Multiple tri-state buffers on a sin-gle wire.
Clk Din
Dout[3]
Dout[1]
Dout[0]
Dout[2]
D Q
D Q
D Q
D Q
FIGURE 1.24 Serial-in, parallel-out shift register.
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Digital Logic 31
On each rising clock edge, a new serial input bit is clocked into the first flop, and each flop in suc-cession loads its new value based on its predecessor’s value. At any given time, the parallel output of an N-bit shift register reflects the state of the last N bits shifted in up to that time. In this example (N = 4), a serial stream of bits collected in four clock cycles can be operated upon as a unit of four bits once every fourth cycle. As shown, data is shifted in MSB first, because Dout[3] is shown in the last bit position. Such a simple transformation is useful, because it is often more practical to commu-nicate digital data in serial form where only one bit of information is sent per clock cycle, but im-practical to operate on that data serially. An advantage of serial communication is that fewer wires are required as compared to parallel. Yet, parallel representation is important because arithmetic logic can get overly cumbersome if it has to keep track of one bit at a time. A parallel-in, serial-out shift register is very similar, as shown in Fig. 1.25, with the signals connected for MSB first opera-tion to match the previous example.
Four flops are used here as well. However, instead of taking in one bit at a time, all flops are loaded when the load signal is asserted. The 2-to-1 muxes are controlled by the load signal and de-termine if the flops are loaded with new parallel data or shifted serial data. Over each of the next four clock cycles, the individual bits are shifted out one at a time. If these two shift register circuits were connected together, a crude serial data communications link could be created whereby parallel data is converted to serial and then back to parallel at each end.
Dout
Clk
D Q
D Q
D Q D
Q Load
Din[0] Din[1] Din[2] Din[3]
FIGURE 1.25 Parallel-in, serial-out shift register.
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