FLIP-FLOPS AND LATCHES

Logic alone does not a system make. Boolean equations provide the means to transform a set of in-puts into deterministic results. However, these equations have no ability to store the results of previ-ous calculations upon which new calculations can be made. The preceding adder logic continually recalculates the sum of two inputs. If either input is removed from the circuit, the sum disappears as well. A series of numbers that arrive one at a time cannot be summed, because the adder has no means of storing a running total. Digital systems operate by maintaining state to advance through se-quential steps in an algorithm. State is the system’s ability to keep a record of its progress in a partic-ular sequence of operations. A system’s state can be as simple as a counter or an accumulated sum.

State-full logic elements called flip-flops are able to indefinitely hold a specific state (0 or 1) until a new state is explicitly loaded into them. Flip-flops load a new state when triggered by the transition of an input clock. A clock is a repetitive binary signal with a defined period that is composed of 0 and 1 phases as shown in Fig. 1.10. In addition to a defined period, a clock also has a certain duty cy-cle, the ratio of the duration of its 0 and 1 phases to the overall period. An ideal clock has a 50/50 duty cycle, indicating that its period is divided evenly between the two states. Clocks regulate the operation of a digital system by allowing time for new results to be calculated by logic gates and then capturing the results in flip-flops.

There are several types of flip-flops, but the most common type in use today is the D flip-flop.

Other types of flip-flops include RS and JK, but this discussion is restricted to D flip-flops because of their standardized usage. A D flip-flop is often called a flop for short, and this terminology is used throughout the book. A basic rising-edge triggered flop has two inputs and one output as shown in Fig. 1.11a. By convention, the input to a flop is labeled D, the output is labeled Q, and the clock is represented graphically by a triangle. When the clock transitions from 0 to 1, the state at the D input is propagated to the Q output and stored until the next rising edge. State-full logic is often described through the use of a timing diagram, a drawing of logic state versus time. Figure 1.11b shows a basic flop timing diagram in which the clock’s rising edge triggers a change in the flop’s state. Prior to the rising edge, the flop has its initial state, Q₀, and an arbitrary 0 or 1 input is applied as D₀. The rising edge loads D₀ into the flop, which is reflected at the output. Once triggered, the flop’s input can change without affecting the output until the next rising edge. Therefore, the input is labeled as

“don’t care,” or “xxx” following the clock’s rising edge.

Logic 1

Logic 0

Time

0 Phase 1 Phase 0 Phase 1 Phase

Period

Finite transition time of real clock signal

FIGURE 1.10 Digital clock signal.

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Digital Logic 19

Rising-edge flops are the norm, although some flops are falling-edge triggered. A falling-edge triggered flop is indicated by placing an inversion bubble at the clock input as shown in Fig. 1.12.

Operation is the same, with the exception that the polarity of the clock is inverted. The remainder of this discussion assumes rising-edge triggered flops unless explicitly stated otherwise.

There are several common feature enhancements to the basic flop, including clock-enable, set, and clear inputs and a complementary output. Clock enable is used as a triggering qualifier each time a rising clock edge is detected. The D input is loaded only if clock enable is set to its active state. Inputs in general are defined by device manufacturers to be either active-low or active-high. An active-low signal is effective when set to 0, and an active-high signal is effective when set to 1. Sig-nals are assumed to be active-high unless otherwise indicated. Active-low inputs are commonly indi-cated by the same inversion bubble used to indicate a falling-edge clock. When a signal is driven to its active state, it is said to be asserted. A signal is de-asserted when driven to its inactive state. Set and clear inputs explicitly force a flop to a 1 or 0 state, respectively. Such inputs are often used to ini-tialize a digital system to a known state when it is first turned on. Otherwise, the flop powers up in a random state, which can cause problems for certain logic. Set and clear inputs can be either synchro-nous or asynchrosynchro-nous. Synchrosynchro-nous inputs take effect only on the rising clock edge, while asynchro-nous inputs take effect immediately upon being asserted. A complementary output is simply an inverted copy of the main output.

A truth table for a flop enhanced with the features just discussed is shown in Table 1.10. The truth table assumes a synchronous, active-high clock enable (EN) and synchronous, active-low set and clear inputs. The rising edge of the clock is indicated by the ↑ symbol. When the clock is at either static value, the outputs of the flop remain in their existing states. When the clock rises, the D, EN, , and inputs are sampled and acted on accordingly. As a general rule, conflicting infor-mation such as asserting and at the same time should be avoided, because unknown re-sults may arise. The exact behavior in this case depends on the specific flop implementation and may vary by manufacturer.

A basic application of flops is a binary ripple counter. Multiple flops can be cascaded as shown in Fig. 1.13 such that each complementary output is fed back to that flop’s input and also used to clock the next flop. The current count value is represented by the noninverted flop outputs with the first flop representing the LSB. A three-bit counter is shown with an active-low reset input so that the counter can be cleared to begin at zero. The counter circuit diagram uses the standard convention of

D Q

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20 Digital Fundamentals

showing electrical connectivity between intersecting wires by means of a junction dot. Wires that cross without a dot at their intersection are not electrically connected.

The ripple counter’s operation is illustrated in Fig. 1.14. Each bit starts out at zero if RESET is as-serted. Counting begins on the first rising edge of CLK following the de-assertion of RESET. The LSB, Q[0], increments from 0 to 1, because its D input is driven by the complementary output, which is 1. The complementary output transitions to 0, which does not trigger the Q[1] rising-edge flop, but IT does set up the conditions for a trigger after the next CLK rising edge. When CLK rises again, Q[0] transitions back to 0, and Q[0] transitions to 1, forming a rising edge to trigger Q[1], which loads a 1. This sequence continues until the count value reaches 7, at which point the counter rolls over to zero, and the sequence begins again.

An undesirable characteristic of the ripple counter is that it takes longer for a new count value to stabilize as the number of bits in the counter increases. Because each flop’s output clocks the next flop in the sequence, it can take some time for all flops to be updated following the CLK rising edge.

Slow systems may not find this burdensome, but the added ripple delay is unacceptable in most high-speed applications. Ways around this problem will be discussed shortly.

TABLE 1.10 Enhanced Flop Truth Table

Clock D EN CLR SET Q Q

0 X X X X Qs t a t i c

↑ 0 0 1 1 Qs t a t i c

↑ 0 1 1 1 0 1

↑ 1 1 1 1 1 0

↑ X X 0 1 0 1

↑ X X 1 0 1 0

↑ X X 0 0 ? ?

1 X X X X Qs t a t i c

D Q

CLR

Q D

Q

CLR

Q D

Q

CLR Q

RESET CLK

Q[0] Q[1] Q[2]

FIGURE 1.13 Three-bit ripple counter.

Q_static Q_static

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Digital Logic 21

A relative of the flop is the D-type latch, which is also capable of retaining its state indefinitely. A latch has a D input, a Q output, and an enable (EN) signal. Whereas a flop transfers its input to its output only on the active clock edge, a latch continuously transfers D to Q while EN is active.

Latches are level sensitive, whereas flops are edge sensitive. A latch retains its state while EN is in-active. Table 1.11 shows the latch’s truth table. Latches are simpler than flops and are unsuited to many applications in which flops are used. Latches would not substitute for flops in the preceding ripple counter example because, while the enable input is high, a continuous loop would be formed between the complementary output and input. This would result in rapid, uncontrolled oscillation at each latch during the time that the enable is held high.

Latches are available as discrete logic elements and can also be assembled from simpler logic gates. The Boolean equation for a latch requires feeding back the output as follows:

When EN is high, D is passed to Q. Q then feeds back to the second AND function, which maintains the state when EN is low. Latches are used in designs based on older technology that was conceived when the latch’s simplicity yielded a cost savings or performance advantage. Most state-full ele-ments today are flops unless there is a specific benefit to using a latch.