INTEL 8051 MICROCONTROLLER FAMILY

Following their success in the microprocessor market, Intel began manufacturing microcontrollers in 1976 with the introduction of the 8048 family. This early microcontroller contains 64 bytes of RAM, 1 kB of ROM, a simple 8-bit microprocessor core, and an 8-bit timer/counter as its sole on-board pe-ripheral. (Subsequent variants, the 8049 and 8050, include double and four times the memory of the 8048, respectively.) The microprocessor consists of a 12-bit program counter, an 8-bit accumulator and ALU, and a 3-bit stack pointer. The 8048 is a complete computer on a single chip and gained a certain amount of fame in the 1980s when it was used as the standard keyboard controller on the -Balch.book Page 125 Thursday, May 15, 2003 3:46 PM

126 Digital Fundamentals

IBM PC because of its simplicity and low cost. The 8048 was manufactured in a 40-pin DIP and could be expanded with external memory and peripherals via an optional external address/data bus.

However, when operated as a nonexpanded single-chip computer, the pins that would otherwise function as its bus were available for general I/O purposes—a practice that is fairly standard on microcontrollers.

Motivated by the popularity of the 8048, Intel introduced the 8051 microcontroller in 1980, which is substantially more powerful and flexible. The 8051’s basic architecture is shown in Fig. 6.3. It contains 128 bytes of RAM, 4 kB of ROM, two 16-bit timer/counters, and a serial port. Registers within the microprocessor are 8 bits wide except for the 16-bit data pointer (DPTR) and program counter (PC). Memory is divided into mutually exclusive program and data sections that each can be expanded up to 64 kB in size via an external bus. Expansion is accomplished by borrowing pins from two of the four 8-bit I/O ports. Intel manufactured several variants of the 8051. The 8052 dou-bled the amount of on-chip memory to 256 bytes of RAM and 8 kB of ROM and added a third timer.

The 8031/8032 are 8051/8052 chips without on-board ROM. The 8751/8752 are 8051/8052 devices with EPROM instead of mask ROM. As time went by and the popularity of the 8051 family in-creased, other companies licensed the core architecture and developed many variants with differing mixes of memory and peripherals.

Ports 0 through 3 are each eight-bit bidirectional I/O structures that can be used as either general-purpose signals or as dedicated interface signals according to the system configuration. In a single-chip configuration where all memory is contained on board, the four ports may be assigned freely.

Some peripheral functions use these I/O pins, but if a specific function is not required, the pins may be used in a generic manner. Port 3 is the default peripheral port where pins are used for the serial port’s transmit and receive, external interrupt request inputs, counter increment inputs, and external bus expansion control signals. Port 1 is a general-purpose port that is also assigned for additional pe-ripheral support signals when an 8051 variant contains additional pepe-ripheral functions beyond what can be supported on port 3 alone.

In a multichip configuration where memory and/or additional peripherals are added externally, ports 0 and 2 are used for bus expansion. Port 0 implements a multiplexed address/data bus where the 8051 first drives the lower eight address bits and then either drives write-data or samples redata in a conventional bidirectional redata bus scheme. In this standard configuration, the lower ad-dress bits, A[7:0], are latched externally by a discrete logic chip (generally a 74LS373 or similar), and the 8051 drives an address latch enable (ALE) signal to control this latch as shown in Fig. 6.4.

This multiplexed address/data scheme saves precious pins on the microcontroller that can be used

Special

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Instructive Microprocessors and Microcomputer Elements 127

for valuable I/O functions. Some applications may suffice with just an eight-bit external address bus.

For example, if the only expansion necessary were a special purpose I/O device, 256 bytes would probably be more than enough to communicate with the device. However, some applications de-mand a fully functional 16-bit external address bus. In these situations, port 2 is used to drive the up-per address bits, A[15:8].

The 8051’s microprocessor is very capable for such an early microcontroller. It includes integer multiply and divide instructions that utilize eight-bit operands in the accumulator and B register, and it then places the result back into those registers. The stack, which grows upward in memory, is re-stricted to on-board RAM only (256 bytes at most), so only an eight-bit stack pointer is imple-mented. Aside from the general-purpose accumulator and B registers, the 8051 instruction set can directly reference 8 byte-wide general-purpose registers, numbered R0 through R7, that are mapped as 4 banks in the lower 32 bytes of on-board RAM. The active register bank can be changed at any time by modifying two bank-select bits in the status word. The map of on-board data memory is shown in Table 6.2. At reset, register bank 0 is selected, and the stack pointer is set to 0x07, meaning that the stack will actually begin at location 0x08 when the first byte is eventually pushed. Above the register banks is a 16-byte (128-bit) region of memory that is bit addressable. Microcontroller appli-cations often involve reading status information, checking certain bits to detect particular events, and then triggering other events. Using single bits rather than whole bytes to store status information saves precious memory in a microcontroller. Therefore, the 8051’s bit manipulation instructions can make efficient use of the chip’s resources from both instruction execution and memory usage per-spectives. The remainder of the lower 128-byte memory region contains 80 bytes of general-purpose memory.

The upper 128 bytes of data memory are split into two sections: special-function registers and RAM. Special-function registers are present in all 8051 variants, but their definitions change ac-cording to the specific mix of peripherals in each variant. Some special-function registers are stan-dard across all 8051 variants. These registers are typically those that were implemented on the original 8051/8052 devices and include the accumulator and B registers; the stack pointer; the data pointer; and serial port, timer, and I/O port control registers. Each time a manufacturer adds an on-board peripheral to the 8051, accompanying control registers are added into the special-function memory region.

On variants that incorporate 256 bytes of on-board RAM, the upper 128 bytes are also mapped into a parallel region alongside the function registers. Access between RAM and special-function registers is controlled by the addressing mode used in a given instruction. Special-special-function registers are accessed with direct addressing only. Therefore, such an instruction must follow the op-code with an eight-bit address. The upper 128 bytes of RAM are accessed with indirect addressing only. Therefore, such an instruction must reference one of the eight general-purpose registers (R0

8051

FIGURE 6.4 8051 system with external address latch.

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128 Digital Fundamentals

through R7 in the currently selected bank) whose value is used to index into that portion of RAM.

The lower 128 bytes of RAM are accessible via both direct and indirect addressing.

The 8051 is a good study in maximizing the capabilities of limited resources. Access to external memory is supported through a variety of indirect and indexed schemes that provide an option to the system designer of how extensive an external bus is implemented. Indirect access to external data memory is supported in both 8- and 16-bit address configurations. In the 8-bit mode, R0 through R7 are used as memory pointers, and the resulting address is driven only on I/O port 0, freeing port 2 for uses other than as an address bus. The DPTR functions as a pointer into data memory in 16-bit mode, enabling a full 64-kB indirect addressing range. Indexed access to external program memory is supported by both the DPTR and the PC. Being program memory (ROM), only reads are sup-ported. Both DPTR and PC can serve as index base address registers, and the current value in the ac-cumulator serves as an offset to calculate a final address of either DPTR+A or PC+A.

The 8051’s external bus interface is asynchronous and regulated by four basic control signals:

ALE, program storage enable (PSEN*), read enable (RD*), and write enable (WR*). Figure 6.5 shows the interaction of these four control signals and the two bus ports: ports 0 and 2. Recall that ALE causes an external latch to retain A[7:0] that is driven from port 0 during the first half of the ac-cess and prior to port 0 transitioning to a data bus role. The timing delays noted are for a standard 12-MHz operating frequency (the highest frequency supported by the basic 8051 devices, although certain newer devices can operate at substantially faster frequencies).^*

TABLE 6.2Memory Map of On-Board Data Memory

Memory Range Range Size Purpose Addressing Mode(s)

0x80–0xFF 128 bytes General-purpose RAM (except 8051) Indirect only 0x80–0xFF 128 bytes Special-function registers Direct only 0x30–0x7F 80 bytes General-purpose RAM Direct/indirect 0x20–0x2F 16 bytes Bit-addressable RAM/general Direct/indirect 0x18–0x1F 8 bytes Register bank 3/general Direct/indirect 0x10–0x17 8 bytes Register bank 2/general Direct/indirect 0x08–0x0F 8 bytes Register bank 1/general Direct/indirect 0x00–0x07 8 bytes Register bank 0/general Direct/indirect

* Embedded Controller Handbook, Vol. I, Intel, 1988, pp. 10-6 through 10-9.

Port 0 ALE

RD*

PSEN*

A[7:0]

Address to valid instruction in: 302 ns WR*

Port 2 A[15:8]

Din[7:0] A[7:0]

A[15:8]

Din[7:0] A[7:0]

A[15:8]

Dout[7:0]

Address to valid data in: 585 ns Address to write complete: 603 ns FIGURE 6.5 8051 bus interface timing.

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Although the specific timing delays of program memory and data memory reads are different, they exhibit the same basic sequence of events. (More time is allowed for data reads than for instruc-tion reads from program memory.) Therefore, if the engineer properly accounts for the timing varia-tions by selecting memory and logic components that are fast enough to satisfy the PSEN* and RD*

timing specifications simultaneously, program and data memory can actually be merged into a uni-fied memory space external to the chip. Such unification can be performed by generating a general memory read enable, MRE*, that is the AND function of PSEN* and RD*. In doing so, whenever ei-ther read enable is driven low by the 8051, MRE* will be low. This can benefit some applications by turning the 8051 into a more general-purpose computing device that can load a program into its

“data memory” and then execute that same program from “program memory.” It also enables in-dexed addressing to operate on data memory, which normally is restricted to indirect addressing as discussed previously.

Timers such as those found in the 8051 are useful for either counting external events or triggering low-frequency events themselves. Each timer can be configured in two respects: whether it is a timer or counter, and how the count logic functions. The selection of timer versus counter is a decision be-tween incrementing the count logic based on the microcontroller’s operating frequency or on an ex-ternal event sensed via an input port pin. The 8051’s inex-ternal logic runs in a repetitive pattern of 12 clock cycles in which 1 machine cycle consists of 12 clock cycles. Therefore, the count logic incre-ments once each machine cycle when in timer mode. When in counter mode, a low-to-high transi-tion (rising edge) on a designated input pin causes the counter to increment. The counter can be configured to generate an interrupt each time it rolls over from its maximum count value back to its starting value. This interrupt can be used to either trigger a periodic maintenance routine at regular intervals (timer mode) or to take action once an external event has occurred a set number of times (counter mode). If not configured to generate an interrupt, the software can periodically poll the timer to see how many events have occurred or how much time has elapsed.

The timers inherently possess two 8-bit count registers that can be configured in a variety of ways as shown in Fig. 6.6. A timer can be configured as a conventional 16-bit counter, as two 8-bit

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counters, as a single 8-bit counter with a 5-bit prescaler, and as a single 8-bit counter with an 8-bit reload value. The first two modes mentioned are straightforward: the timers count from 0 to either 65,535 (16-bit) or 255 (8-bit) before rolling over and perhaps generating an interrupt. The third mode is similar, but the 8-bit counter increments only once every 32 machine cycles. The 5-bit (2⁵ = 32) prescaler functions as a divider ahead of the main counter. Apparently, the main reason for in-cluding this mode was to retain function compatibility with the 8048’s prescaled timer. The fourth mode is interesting, because the 8-bit counter is reloaded with an arbitrary 8-bit value rather than 0 after reaching its terminal count value (255). When operated in timer mode, this feature enables the timer to synthesize a wide range of low-frequency periodic events. One very useful periodic event is an RS-232 bit-rate generator. A commonly observed 8051 operating frequency is 11.0592 MHz.

When this frequency is divided by 12, a count increment rate of 921.6 kHz is obtained. Further di-viding this frequency by divisors such as 96 or 384 yields the standard RS-232 bit rates 9.6 kbps and 2.4 kbps. A divisor of 384 cannot be implemented in an 8-bit counter. Instead, a selectable ÷16 or

÷32 counter is present in the serial port logic that generates the final serial bit rate.

The 8051’s on-board serial port implements basic synchronous or asynchronous transmit and re-ceive shift-register functionality but does not incorporate hardware handshaking of the type used in RS-232 communications. Serial transmission is initiated by writing the desired data to a transmit register. Incoming data is placed into a receive register, and an interrupt can be triggered to invoke a serial port ISR. The serial port can be configured in one of four modes, two of which are higher-fre-quency fixed bit rates, and two of which are lower-frehigher-fre-quency variable bit rates established by the rollover characteristics of an on-board timer. Mode 0 implements a synchronous serial interface where the “receive data” pin is actually bidirectional and a transmit clock is emitted on the “transmit data” pin. This mode operates on 8-bit data and a fixed bit rate of 1/12 the operating frequency.

Mode 1 implements an asynchronous transmit/receive serial port where ten bits are exchanged for every byte: a start bit, eight data bits, and a stop bit. The bit-rate is variable according to a timer roll-over rate. Mode 3 is very similar to mode 1, with the added feature that a ninth data bit is added to each byte. This extra data bit can be used for parity in an RS-232 configuration or for another appli-cation-specific purpose. These two modes can be used to implement an RS-232 serial port without hardware handshaking. Software-assisted hardware handshaking could be added using general I/O pins on the 8051. Mode 2 is identical to mode 3 except for its fixed bit rate at either 1/32 or 1/64 the operating frequency. Modes 1 and 3 can be made to operate at standard RS-232 bit rates from 19.2 kbps on downward with the aforementioned 11.0592 MHz operating frequency. A selectable

÷16 or ÷32 counter within the serial port logic combines with the timer rollover to achieve the de-sired serial bit rate.

Intel’s 8051 architecture has been designed into countless applications in which a small, embed-ded computer is necessary to regulate a particular process. The original 40-pin devices are still com-monly used and found in distributors’ warehouses, but a host of newer devices are popular as well.

Some of these variants are larger and more capable than the original and include more I/O ports, on-board peripherals, and memory. Some variants have taken the opposite direction and are available in much smaller packages (e.g., 20 pins) with low power consumption for battery-powered applica-tions. There are even special versions of the 8051 that are radiation hardened for space and military applications. Companies that manufacture 8051 variants include Atmel, Maxim (formerly Dallas Semiconductor), and Philips. Atmel manufactures a line of small, low-power 8051 products. Maxim offers a selection of high-speed 8051 microcontrollers that run at up to 33 MHz with a 4-cycle archi-tecture, as compared to 12 in the original 8051. Philips has a broad 8051 product line with a variety of peripherals to suit many individual applications.

The mature ROM-less 8031/8032 members of the 8051 family can be ordered through many mail order retail electronics outlets for only a few dollars apiece. The equally mature 8751/8752 EPROM devices can also be found from many of these same sources, though at a higher price as a result of -Balch.book Page 130 Thursday, May 15, 2003 3:46 PM

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the expense of the ceramic DIP in which they are most often found. More specialized 8051 variants may be available only through manufacturers’ authorized distributors.