INTEL 8086 16-BIT MICROPROCESSOR FAMILY

Intel moved up to a 16-bit microprocessor, the 8086, in 1978—just two years after introducing the 8085 as an enhancement to the 8080. The “x86” family is famous for being chosen by IBM for their original PC. As PCs developed during the past 20 years, the x86 family grew with the industry—first to 32 bits (80386, Pentium) and more recently to 64 bits (Itanium). While the 8086 was a new archi-tecture, it retained certain architectural characteristics of the 8080/8085 such that assembly language programs written for its predecessors could be converted over to the 8086 with little or no modifica-tion. This is one of the key reasons for its initial success.

The 8086 contains various 16-bit registers as shown in Fig. 6.9, some of which can be manipu-lated one byte at a time. AX, BX, CX, and DX are general-purpose registers that have alternate func-tions and that can be treated as single 16-bit registers or as individual 8-bit registers. The accumulator, AX, and the flags register serve their familiar functions. BX can serve as a general pointer. CX is a loop iteration count register that is used inherently by certain instructions. DX is used as a companion register to AX when performing certain arithmetic operations such as integer division or handling long integers (32 bits).

The remaining registers are pointers of various types that index into the 8086’s somewhat awk-ward segmented memory structure. Despite being a 16-bit microprocessor with no register exceed-ing 16 bits in size, Intel recognized the need for more than 64 kB of addressable memory in more advanced computers. One megabyte of memory space was decided upon as a sufficiently large ad-dress space in the late 1970s, but the question remained of how to access that memory with 16-bit pointers. Intel’s solution was to have programmers arbitrarily break the 1 MB address space into multiple 64-kB special-purpose segments—one for instructions (code segment), two for data (pri-mary data and “extra” data), and one for the stack. Memory operations must reference one of these defined segments, requiring only a 16-bit pointer to address any location within a given segment.

Segments can be located anywhere in memory, as shown in Fig. 6.10, and can be moved at will to provide flexibility for different applications. Additionally, there is no restriction on overlapping of segments.

Each segment register represents the upper 16 bits of a 20-bit pointer (2²⁰ = 1 MB) where the lower 4 bits are fixed at 0. Therefore, a segment register directly points to an arbitrary location in 1 MB of memory on a 16-byte boundary. A pointer register is then added to the 20-bit segment ad-dress to yield a final 20-bit adad-dress, the effective adad-dress, with which to fetch or store data. Algebra-ically, this relationship is expressed as: effective address = (segment pointer × 16) + offset pointer.

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AH AL

AX Accumulator

BH BL

BX Base

CH CL

CX Count

DH DL

DX Data

8 bits 16 bits 8 bits

SP Stack pointer

BP Base pointer

SI Source index

DI Destination index

IP Instruction pointer Flags ALU status flags

CS Code segment

DS Data segment

SS Stack segment

ES Extra data segment

FIGURE 6.9 8086 register set.

CS

DS SS ES

inaccessible memory outside

of currently defined segments

Data segment Stack segment

Code segment Extra data segment overlap

Memory bottom: 0x00000 Memory top: 0xFFFFF

FIGURE 6.10 8086 segments.

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136 Digital Fundamentals

Inside the microprocessor, this math is performed by shifting the segment pointer (0x135F) left by four bits and then adding the offset pointer (0x0102) as shown below.

This segmented addressing scheme has some awkward characteristics. First, programs must orga-nize their instructions and data into 64-kB chunks and properly keep track of which portions are be-ing accessed. If data outside of the current segments is desired, the appropriate segment register must be updated. Second, the same memory location can be represented by multiple combinations of segment and offset values, which can cause confusion in sorting out which instruction is accessing which location in memory. Nonetheless, programmers and the manufacturers of their development tools have figured out ways to avoid these traps and others like them.

Instructions that reference memory implicitly or explicitly determine which offset pointer is added to which segment register to yield the desired effective address. For example, a push or pop instruction inherently uses the stack pointer in combination with the stack segment register. How-ever, an instruction to move data from memory to the accumulator can use one of multiple pointer registers relative to any of the segment registers.

The 8086’s reset and interrupt vectors are located at opposite ends of the memory space. On reset, the instruction pointer is set to 0xFFFF0, and the microprocessor begins executing instructions from this address. Therefore, rather than being a true vector, the 16-byte reset region contains normal exe-cutable instructions. The interrupt vectors are located at the bottom of the memory space starting from address 0, and there are 256 vectors, one for each of the 256 interrupt types. Each interrupt vec-tor is composed of a 2-byte segment address and a 2-byte offset address, from which a 20-bit effec-tive address is calculated. When the 8086’s INTR pin is driven high, an interrupt acknowledge process begins via the INTA* output pin. The 8086 pulses INTA* low twice and, on the second pulse, the interrupting peripheral drives an interrupt type, or vector number, onto the eight lower bits of the data bus. The vector number is used to index into the interrupt vector table by multiplying it by 4 (shifting left by two bits), because each vector consists of four bytes. For example, interrupt type 0x03 would cause the microprocessor to fetch four bytes from addresses 0x0C through 0x0F.

Interrupts triggered by the INTR pin are all maskable via an internal control bit. Software can also trigger interrupts of various types via the INT instruction. A nonmaskable interrupt can be triggered by external hardware via the NMI pin. NMI initiates the type-2 interrupt service routine at the ad-dress indicated by the vector at 0x08-0x0B.

Locating the reset boot code at the top of memory and the interrupt vectors at the bottom often leads to an 8086 computer architecture with ROM at the top and some RAM at the bottom. ROM must be at the top, for obvious reasons. Placing the interrupt vector table in RAM enables a flexible system in which software applications can install their own ISRs to perform various tasks. On the original IBM PC platform, it was not uncommon for programs to insert their own ISR addresses into certain interrupt vectors located in RAM. The system timer and keyboard interrupts were common objects of this activity. Because the PC’s operating system already implemented ISRs for these inter-rupts, the program could redirect the interrupt vector to its own ISR and then call the system’s de-fault ISR when its own ISR completed execution. If properly done, this interrupt chaining process could add new features to a PC without harming the existing housekeeping chores performed by the standard ISRs. Chaining the keyboard interrupt could enable a program that is normally dormant to pop up each time a particular key sequence is pressed.

1 3 5 F 0 Segment pointer

+ 0 1 0 2 Offset pointer

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Despite its complexity and 16-bit processing capability, the 8086 was originally housed in a 40-pin DIP—the same package used for most 8-bit processors of the time. Intel chose to use a multi-plexed address/data scheme similar to that used on the 8051 microcontroller, thereby saving 16 pins.

The 8086’s 20-bit address bus is shared by the data bus on the lower 16 bits and by status flags on the upper 4 bits. Combined with additional signals, these status flags control the microprocessor’s bus interface. As with Intel’s other microprocessors, the 8086 contains separate address spaces for mem-ory and I/O devices. A control pin on the chip indicates whether a transaction is memmem-ory or I/O.

While the memory space is 1 MB in size, the I/O space is only 64 kB. The 8086 bus interface oper-ates in one of two modes, minimum and maximum, determined by a control pin tied either high or low, respectively. In each of these two modes, many of the control and status pins take on different functions. In minimum mode, the control signals directly drive a standard “Intel-style” bus similar to that of the 8080 and 8051, with read and write strobes and address latch enable. Other signals in-clude a READY signal for inserting wait states for slow peripherals and a bus grant/acknowledge mechanism for supporting DMA or similar bus-sharing peripherals. Minimum mode is designed for smaller systems in which little address decoding logic is necessary to interface the 8086 to memory and peripherals devices. Maximum mode is designed for larger systems where an Intel companion chip, the 8288 bus controller, integrates more complex bus control logic onto an off-the-shelf IC. In maximum mode, certain status and control pins communicate more information about what type of transaction is being performed at any given time, enabling the 8288 to take appropriate action.

The 8086’s 16-bit data bus is capable of transacting a single byte at a time for purposes of access-ing byte-wide peripherals. One early advantage of the 8086 was its backward bus compatibility with the 8080/8085. In the 1970s, Intel manufactured a variety of I/O peripherals such as timers and par-allel I/O devices for their eight-bit microprocessors. The 8086’s ability to perform byte-wide trans-actions enabled easy reuse of existing eight-bit peripheral products. Two signals, byte high enable (BHE*) and address bit zero (A[0]), communicate the width and active byte of each bus transaction as shown in Table 6.3.

Intel’s microprocessors follow the little-endian byte ordering convention. Little-endian refers to the practice of locating the LSB of a multibyte quantity in a lower address and the MSB in a higher address. In a little-endian 16-bit microprocessor, the value 0x1234 would be stored in memory by lo-cating 0x12 into address 1 and 0x34 into address 0. Big-endian is the opposite: locating the LSB in the higher address and the MSB in the lower address. Therefore, a big-endian 16-bit microprocessor would store 0x12 into address 0 and 0x34 into address 1. To clarify the difference, Table 6.4 shows little-endian versus big-endian for 16- and 32-bit quantities as viewed from a memory chip’s per-spective. Here, ADDR represents the base address of a multibyte data element.

Proponents of little-endian argue that it makes better sense, because the low byte goes into the low address. Proponents of big-endian argue that it makes better sense, because data is stored in TABLE 6.3 8086 Bus Sizing

BHE* A[0] Transaction Type

0 0 16-bit transaction

0 1 8-bit transaction: high byte (odd address) 1 0 8-bit transaction: low byte (even address)

1 1 Undefined

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138 Digital Fundamentals

memory as you would read and interpret it. The choice of “endianness” is rather religious and comes down to personal preference. Of course, if you are designing with a little-endian microprocessor, life will be made simpler to maintain the endianness consistently throughout the system.

At the time of the 8086’s introduction, 16-bit desktop computer systems were almost unheard of and could be substantially more expensive than 8-bit systems as a result of the increased memory size required to support the larger bus. To alleviate this problem and speed market acceptance of its archi-tecture, Intel introduced the 8088 microprocessor in 1979, which was essentially an 8086 with an eight-bit data bus. A lower-cost computer system could be built with the 8088, because fewer EPROM and RAM chips were necessary, system logic did not have to deal with two bytes at a time, and less circuit board wiring was required. A tremendous benefit to Intel in designing the 8088 was the fact that it was chosen by IBM as the low-cost 16-bit heart of the original PC/XT desktop computer, thereby locking the x86 microprocessor family into the IBM PC architecture for decades to come.

A variety of companion chips were developed by Intel to supplement the 8086/8088. Among these was the 8087 math coprocessor that enhanced the 8086’s computational capabilities with float-ing-point arithmetic operations. Floating-point arithmetic refers to a computer’s handling of real numbers as compared to integers. The task of adding or multiplying two real numbers of arbitrary magnitude is far more complex than similar integer operations. Certain applications such as scien-tific simulations and realistic games that construct a virtual reality world make significant use of floating-point operations. The 8087 is a coprocessor rather than a peripheral, because it sits on the microprocessor bus in parallel with the 8086 and watches for special floating-point instructions.

These instructions are then executed automatically by the 8087 rather than having to wait for the 8086 to request an operation. The 8086 was designed with the 8087’s existence in mind and ignores instructions destined for the 8087. Therefore, software must specifically know if a math coprocessor is installed to run correctly. Many programs that ran on older systems with or without a coprocessor would first test to see if the coprocessor was installed and then execute either an optimized set of routines for the 8087 or a slower set of routines that emulated the floating-point operations via con-ventional 8086 instructions.

As the x86 family developed, the optional math coprocessor was eventually integrated alongside the integer processor on the same silicon chip. The 8087 gave way to the 80287 and 80387 when the 80286 and 80386 microprocessors were produced. When Intel introduced the 80486, the coproces-sor, or floating-point unit (FPU), was integrated on chip. This integration resulted in a somewhat more expensive product, so Intel released a lower-cost 80486SX microprocessor without the copro-cessor. An 80487SX was made available to upgrade systems originally sold with the 80486SX chips, but the overall situation proved somewhat chaotic with various permutations of microprocessors and systems with and without coprocessors. Starting with the Pentium, all of Intel’s high-end micropro-cessors contain integrated FPUs. This trend is not unique to Intel. High-performance microproces-sors in general began integrating the FPU at roughly the same time because of the performance benefits and the overall simplicity of placing the microprocessor and FPU onto the same chip.

TABLE 6.4 Little-Endian vs. Big-Endian

Value Endianness ADDR+0 ADDR+ 1 ADDR+2 ADDR+3

0x1234 Little 0x34 0x12 X x

0x1234 Big 0x12 0x34 X x

0x12345678 Little 0x78 0x56 0x34 0x12

0x12345678 Big 0x12 0x34 0x56 0x78

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