The Multibus System Bus
2.3 BUS SIGNAL DEFINITIONS AND OPERATION OVERVIEW
2.3.5 Interrupt Lines
An interrupt is typically used in a real-time execution-type system in which an external event must be acted upon with minimal delay. Any system with inter-rupt capability must have a set of interinter-rupt servicing routines in its executive software. Each of these interrupt service routines is a task activated by a par-ticular interrupt level or number; this type of control is well suited to the machine and process control marketplace. The microprocessor is the destination of all interrupts. Each of the interrupt sources is assigned an interrupt number which determines its priority level. When multiple interrupts occur at the same time, the interrupt with the highest priority is serviced first.
Most microprocessors have a hardware interrupt input pin which, when acti-vated, causes the program currently being executed to be automatically sus-pended. Then the state of the machine is saved and the program ~xecution
control is transferred to an interrupt service routine that corresponds to the device that caused the interrupt. The particular interupt service routine is cho-sen by the hardware, which tells the microprocessor where to go in the progam by sending it an interrupt vector address. The interrupt vector address is not necessarily the exact memory address of the starting location of the service rou-tine; some microprocessors modify the address before using it. The resultant address is then used as a lookup vector in a table of jump commands which points to the various service routines.
The basic structure of the Multibus interrupt system is shown in Fig. 2-13.
The microprocessor in this diagram is controlling some external machine and processes. The machine will generate interrupts when service is needed. The microprocessor then stops executing its current progam and starts executing the interrupt service routine for that device. After it has completed servicing the machine, the microprocessor signals the I/O device to turn off its interrupt and then returns to the program it was previously executing.
The interrupt lines can be broken down into two groups:
Interrupt request INTO*-INT7* Interrupt 0-7
Interrupt hold INTA* Interrupt acknowledge
MACHI NE 1
SYSTEM'S REAL-TIME SCHEDU L E R
FIGURE 2-13 Interrupt system structure.
INTERRUPT REQUEST
PROCESS SERVICE ROUTINE
MACHINE 2
The interrupt request lines (INTO* to INT7*) are used by any bus module to activate an interrupt service request from the system master. The requesting device activates the interrupt signal and keeps it active until serviced. INTO* . has the highest priority.
INTERRUPT ACKNOWLEDGE
Interrupt acknowledge (INT A *) is generated during interrupt cycles on the bus.
It is used to freeze the interrupt status of all the interrupt controllers in the system and then get the interrupt vector address from another module in the system. The Multibus supports two types of interrupt implementation schemes:
non-bus-vectored and bus-vectored.
NON-BUS-VECTORED INTERRUPTS
Non-bus-vectored (NBV) interrupts are handled totally on the bus master and do not require the Multibus interface for the interrupt vector address. The inter-rupt vector address is generated by the interinter-rupt controller on the bus master and transferred to the microprocessor over the local bus. The device that gen-erates the interrupts can reside on the bus master or on a bus slave module. In the 'latter case it uses the Multibus interrupt request lines (INTO* to INT7*) to
48 THE MUL TIBUS FAMILY OF BUS STRUCTURES
generate its interrupt requests to the bus master. In both cases the bus master performs its own interrupt operation by generating the interrupt vector address locally and executing the interrupt service routine. This routine will service the interrupting device and command it to remove the interrupt request. Figure 2-14 shows two examples of NBV interrupt implementation, one with the inter-rupting device on the bus master module and one with the device on a bus slave module.
BUS-VECTORED INTERRUPTS
For bus-vectored (BV) interrupts the bus master requires the aid of the rupting module. After receiving an interrupt, the bus master requests the inter-rupting bus module to send the appropriate interrupt vector address. The
BUS MASTER BUS SLAVE
MICROPROCESSOR
I
MEMORY
I
r l
I/ODEVICE INTR
J r
INTERRUPT I/O
CONTROLLER DEVICE
2 1 0
A I
BUFFERSI
INTERRUPT BUFFERS+5 V
INT2*
i
-1 1
<: ___________________________
M_U_L_T_IB_U_S __________________________:>
INT2*
/1
i
llo DEVICE NEEDS TO BE SERVICEDTIMING
I
MICROPROCESSOR HAS SERVICING 110 DEVICE AND
FlNISH~
RESETS INTERRUPT REQUEST LINE
FIGURE 2-14 Non-bus-vectored interrupts.
BUS MASTER BUS SLAVE
DATO*- INTERRUPT CONTROLLER INTERRUPT CONTROLLER
DAT7* INT A * signal to request the interrupt vector address.
Figure 2-15 shows a BV interrupt implementation. When the interrupt is requested,
1. The slave interrupt controller notifies the master interrupt controller on the bus master, which causes the microprocessor on the bus master to process the interrupt.
50 THE MULTIBUS FAMILY OF BUS STRUCTURES
2. The microprocessor then generates an INT A * command on the system bus, which freezes the state of the priority of the interrupt logic on all bus mod-ules. Each of the slave interrupt controllers is assigned a unique interrupt controller address.
3. Next the bus master puts the address of the bus slave's interrupt controller on the Multibus address lines (ADR8* to ADRA*) that had the highest-prior-ity interrupt request.
4. The bus master also generates a second INT A * command.
5. The second INT A * command asks the selected interrupt controller to put its interrupt vector address on the Multibus data lines (DATO* to DAT8*).
6. The bus slave activates the XACK* signal when the interrupt vector address on the data lines is valid.
7. This causes the bus master to terminate the interrupt cycle by removing the INT A