Bus Timing

All the timing specifications of the Multichannel bus are described in this sec-tion; they are summarized in Table 3-2. Timing diagrams have been included to show the signal timing relations.

Timing

Ref Parameter description min max Source Note

tl AID line setup to leading edge of 60 T DRDY.

t2 AID line hold after leading edge of 40 T AACC or DACC.

t3 Data mode (A/Dlow) and R/W 60 M

setup to leading edge of DRDY.

t4 A/5 hold after trailing edge of so M

tl2 Trailing edge of DRDY. to leading edge of DRDY. (AID high)

trailing edge of STO. or SRQ.

t19 Trailing edge of STO. or SRQ. to 0 SL S

110 THE MULTIBUS FAMILY OF BUS STRUCTURES

TABLE 3·2 Mulllchannel Bus Timing Speclflcatlons (Conllnued)

Ref Parameter description SA* low to AD15*-ADO*, DRDY*

in high-impedance state

• All times listed are nanoseconds unless otherwise noted.

Timing

min max Source Note

75 SU

• All signals are shown as TTL-type waveforms. (For differential line pairs, the waveform applies to the TTL driver input or receiver output.)

• T refers to the selected talker for a bus cycle.

• L refers to the, or a, selected listener for a bus cycle.

• M refers to the selected master for a bus cycle.

• SL refers to the, or a, selected slave for a bus cycle.

• SU refers to the system supervisor.

1. This timing parameter applies only when there is a message mode transition from address to data mode or from data to address mode. When the mode does not change, the "address not data" line should be held at a constant level.

2. The signals specify the basic bus cycle transfer handshake. Though speCified at 0 ns mini-mum, there is a minimum propagation delay for each parameter relative to the cable length between the talker and the listener. This propagation delay is approximately 2 ns/ft. Because the handshake requires a three-step interlock, the minimum propagation delay is multiplied by 3 to determine the total propagation delay. Thus a talker and listener with a short cable run between them would experience very little propagation delay. However, a talker and listener separated by the maximum length of Multichannel bus cable (50 ft) would experience a total propagation delay of at least 300 ns.

3. These parameters apply in messages where the master is the listener for the data mode por-tion of the message.

4. These parameters apply when a parity error is detected by a listener during a bus cycle. All other assertions of the interrupt lines can be asynchronous to the bus operation.

5. These parameters apply during the bus cycle when the STO or SRQ status register of the device asserting the interrupt line is read during an STO or SRQ poll.

6. The minimum Reset pulse width is 5 ms.

ADDRESS OPERA liON

An address operation is generated by the bus master and received by the bus slaves. The lines involved and the timing relations are shown in Fig. 3-16. The master places address information on the bus a minimum of 60 ns (tl) prior to DRDY* active and sets the A/D line high (address) 200 ns (t^g) and the R/W line low (write) a minimum of 60 ns (t3) prior to DRDY*. After the setup requirements have been met, the master drives DRDY * active. All slaves on the bus respond to the DRDY* by driving AACC active a minimum of 0 ns (t5 )

after receiving DRDY*. Upon receiving AACC active (all slaves have accepted the address), the master removes DRDY* a minimum of 0 ns (t_{6 )} and holds the address 40 ns (t_{2 )} after receiving AACC. The slaves then remove the AACC signal a minimum of 0 ns (ts) to a maximum of 75 ns (ts) from DRDY* inactive.

The next address sent by the master must not occur until a minimum of 250 ns (t 12). The address cycle time t12 and the AACC maximum inactive time ts ensure that the AACC line has settled before the next address is sent.

DATA READ OPERATION

A data read operation transfers data from the slave to the bus master controlling the bus. The lines involved and the timing relations are shown in Fig. 3-17.

active a minimum of 0 ns (t5) after receiving DRDY*. Upon receiving DACC*

active, the slave removes DRDY* a minimum of 0 ns (t6) and holds the data 40 ns (t₂₎ after receiving DACC*. The master then removes the DACC* signal a minimum of 0 ns (t7) from DRDY* inactive. The next data cycle can occur immediately after DACC* is removed. The minimum cycle time is 100 ns (t_{l4 ),} which is the minimum setup and hold time for a data cycle (tl

+

t2).

FIGURE 3-16 Address cycle timing. (Note: For differential line paIrS, level denotes posi-tive portion of differential pair.)

112 THE MULTIBUS FAMILY OF BUS STRUCTURES

FIGURE 3-17 Data read cycle timing. (Note: For differential line pairs, level denotes pos-itive portion of differential pair.)

DATA WRITE OPERATION

A data write operation transfers data from the bus master controlling the bus to the addressed slave. The lines involved and the timing relations are shown in Fig. 3-18. Once the master has completed the address cycle, it sets the R/W line to write mode (R/W

=

low) and the A/D line to data mode (A/D

=

low) a minimum of 60 ns (ts) before driving DRDY* active. The master, which is now the talker, places data information on the bus a minimum of 60 ns (tl )

prior to DRDY* active. After the setup requirements have been met, the master drives DRDY* active. The selected slave responds to the DRDY* by accepting the data and driving DACC* active a minimum of 0 ns (t5) after receiving DRDY*. Upon receiving DACC* active, the master removes DRDY* a mini-mum of 0 ns (t6) and holds the data 40 ns (t2) after receiving DACC*. The selected slave then removes the DACC* signal a minimum of 0 ns (t7) from DRDY* inactive. The next data cycle can occur immediately after DACC* is removed. The minimum cycle time is 100 ns (t14 ), which is the minimum setup and hold time for a data cycle (tl

+

^t2)'

BUS EXCHANGE OPERATION

The bus exchange operation occurs when the supervisor passes bus control over to a bus controller and again when it regains control. The lines involved and the timing relations are shown in Fig. 3-19. When ready to release the bus, the supervisor guarantees that its AID and control drivers are turned off a

Interrupt operations include both STO* and SRQ* timing. Since STO* is used to indicate bus errors as well as device status, additional timing constraints are placed on STO* for transfer error reporting. Figure 3-20 shows the timing

rela-AD15 *-ADO*

FIGURE 3-18 Data write cycle timing. (Note: For differential line pairs, level denotes pos-itive portion of differential pair.)

114 THE MULTIBUS FAMILY OF BUS STRUCTURES

ADlS·-ADO·

DRDY·

DACC·

AACC

SA·

SUPERVISOR DRIVERS

MASTER DRIVERS

I _ _ _ _ _ _ _ ...J I

t15

-SUPERVISOR DRIVERS

FIGURE 3-19 Bus exchange timing. (Note: For differential line pairs, level denotes pos-itive portion of differential pair.)

tions for STO* as a transfer error signal. In the diagram the current data cycle is the cycle that error occurred in. The device that detects the transfer error asserts STO* a minimum of 0 ns (tI6 ) after receiving DRDY* active. AACC or DACC* is driven active a minimum of 0 ns (tl7) after STO* is asserted. The SRQ* signal is removed by reading the device's SRQ register. The SRQ* signal may be removed a minimum of 0 ns (tIS) after the device is selected and the bus is placed in data mode, but it must be removed a maximum of 0 ns (t_I9) prior to the register read DRDY* going inactive. Figure 3-21 shows the timing relations of STO* and SRQ* when used other than parity error. In this case a device may place STO* or SRQ* active anytime on the bus. The SRQ* and STO* signals are removed by reading the device's interrupt register. The signals may be removed a minimum of 0 ns (tIS) after the device is selected and the bus is placed in data mode, but they they must be removed a maximum of

o

^{ns (t}19) prior to the register read DRDY* going inactive.

3.6.6 Receivers. Drivers. and Terminations

In this section the driver type, the receiver loading, and the signal termination requirements are defined. The driver-receiver direct-current (DC) specifica-tions are listed in Table 3-3. Figure 3-22 is a diagram of the three bus driver-receiver configurations supported on the bus. It should be noted that all open collector lines should be received by hysteresis-Schmitt trigger devices, such as

Zl I

R/W _ _ _ _ _ _ _ _ _ _ _ .J I

---,

AID ,

... t I 9 + · J

-DRDY·

I

' - - - t I 8

----~--~---STO·

I

DACC·

\'---11

AACC

\'----FIGURE 3-20 Transfer error interrupt timing. (Note: For differential line pairs, level denotes positive portion of differential pair.)

II I

R/W _ _ _ _ _ _ _ _ _ _ _ ..J I

---,

AID ,

\ ,_---Ill--

^{'+---. 4 -tI9+}

DRDY· \'-_ _ _ _ -1 ' - - - 1 - - - 1

1

STO·

SRO*

\\\\\\\\~

'-~--tI8---...

J---~---I

FIGURE 3-21 Status interrupt timing. (Note: For differential line pairs, level denotes positive portion of differential pair.)

116 THE MUL TIBUS FAMILY OF BUS STRUCTURES

TABLE 3·3 Multichannel Bus DC Speclttcatlon

Minimum driver Maximum receiver requirements, rnA requirements, rnA

Signal Driver Termination^ll Load cap, Load cap,

name type

n

^{High Low pF} High Low pF

ADI5-0* Tristate 110 -5 48 300 0.2 0.8 15

SA* Open coil 1l0/220 N.A.^b 48 300 0.4 0.6 15 Reset* Open coil 1l0/220 N.A. 48 300 0.4 0.6 15 AACC Open colI 1000/2000 N.A. 48 300 0.4 0.6 15 DACC* Open coil 1l0/220 N.A. 48 300 0.4 0.6 15 SRQ* Open coil 1l0/220 N.A. 48 300 0.4 0.6 15 STO. Open coil 1l0/220 N.A. 48 300 0.4 0.6 15 R/W Dif, noninv 220/470 -20 40 300 0.5 0.5 15 R/W/ Dif, iny 470/220 -20 40 300 0.5 0.5 15 A/O Dif, noniny 220/470 -20 40 300 0.5 0.5 15 A/O/ Dif, iny 470/220 -20 40 300 0.5 0.5 15 PB. Dif, noniny 220/470 -20 40 N.A. 0.5 0.5 N.A.

PB*/ Dif, iny 470/220 -20 40 N.A. 0.5 0.5 N.A.

DRDY. Dif, noniny 220/470 -20 40 N.A. 0.5 0.5 N.A.

DRDY./ Dif, iny 470/220 -20 40 N.A. 0.5 0.5 N.A.

"Termination provided only at the physical ends of the interconnect cable. Where the positive termination (pull-up) resistance is different from the negative termination (pull-down) resistance, the positive termination resistance is listed first.

bN.A. = not applicable.

the 74LS14, that have a minimum V_T+ - VT - of 0.4 V. Figure 3-23 is the bus termination schematic diagram for both ends of the cable. This is the only mination on the cable, and it can be supplied by the devices or by special ter-mination modules.

3.7 MECHANICAL CONSIDERATIONS

In this section all the physical and mechanical considerations that a designer requires for proper Multichannel bus implementation are defined. In the fol-lowing sections the Multichannel bus mechanical requirments are set forth.

Dans le document Guidebook Mu tibus Design (Page 125-133)