Address and Chip Select Lines

The address and chip select lines can be divided into two groups:

Class Address Chip selects

Signal Function

MA2-MAO Address lines (2-0) MCSh, MCSO. Chip select lines (1-0)

The baseboard provides the decode logic for the iSBX interface. The logic generates the chip selects for the iSBX Multimodule boards and passes on the

130 THE MUL TlBUS FAMILY OF BUS STRUCTURES

least significant portio.n of the I/O address to the Multimodule board. The board decodes all but the lower-order bits of the I/O address in generating the two iSBX Multimodule board chip selects (MCS1 * and MCSO*). In 8-bit baseboard systems supporting the 8/8 bit mode of the bus specification, the baseboard assigns two blocks of eight I/O port addresses for each iSBX interface it pro-vides. In 16-bit baseboard systems supporting the 16/8 or 16/16 bit mode, the baseboard assigns two blocks of 16 I/O port addresses for each of its iSBX inter-faces. The I/O addresses reserved by the baseboard for each iSBX interface it provides are summarized in Table 4-1. Note that the 8-bit and 16-bit baseboard systems reserve different addresses and that the address assignments are required by Inters iSBX Bus Specification. The IEEE-P595 Bus Specification only recommends these addresses.

ADDRESS

The three address lines MA2 to MAO carry the least significant portion of the binary address of the I/O device location that the baseboard is referencing;

MAO is the least significant bit of the address. The address lines are positive true input lines to the Multimodule board. In 8-bit baseboard systems the MA2 to MAO are mapped directly to the three least significant address bits of the micro-processor. In 16-bit baseboard systems (e.g., one based on an 8086'microproces-sor), MA2 to MAO are mapped to address bit 3 through address bit 1 on the baseboard, since address bit 0 is used in the chip select generation.

The iSBX bus supports both byte and word addressing (Fig. 4-5). A byte (8 bits) location is the smallest addressable unit of storage. There are two types of byte address locations, an even-byte address (address 0 of the baseboard is inac-tive) and an odd-byte address (address 0 of the baseboard is acinac-tive). Two con-secutive byte locations form a word. The iSBX bus in 16/16 bit mode can trans-fer a word if the first byte location of the word is an byte address (an even-word address). If the first byte location of the word is an odd-byte address (an odd-word address), the baseboard must perform two byte accesses and assemble the word.

TABLE 4·1 Baseboard I/O Addressing Assignments for ISBX Bus (Hexadecimal Notation)

8·bit baseboard 16-bit baseboard 16-bit baseboard iSBX Multimodule Chip address (8/8 bit address (16/8 bit address (16/16

connector no. select mode) mode) bit mode)

iSBX 1 MCSO. FO-F7 OAO-OAF OAO,2,4,6,8,A,C,E

MCSh F8-FF OBO-OBF OAI,3,5,7,9,B,D,F

iSBX 2 MCSO. CO-C7 080-08F OAO,2,4,6,8,A,C,E

MCSh C8-CF 090-09F 081,3,5,7,9,B,D,F

iSBX 3 MCSO. BO-B7 060-06F 060,2,4,6,8,A,C,E

MCSI. B8-BF 070-07F 061,3,5,7,9,B,D,F

000- BYTE

FIGURE 4-5 Memory and I/O Address Mapping. (Note: Bus master must break odd-word address access into two byte accesses and reform the word.)

CHIP SELECT LINES

In 8-bit systems, the negative true input lines MCSI * and MCSO* to the iSBX Multimodule board are the result of the baseboard decode logic. This logic decodes the appropriate local bus address bits into the iSBX Multimodule chip select lines, as defined in Fig. 4-6. The chip select signals, along with the I/O command signals, enable communication with the iSBX Multimodule boards.

In 16-bit systems, the chip select signals optionally have two definitions: one for the 16/8 bit mode and one for the 16/16 bit mode. These options are select-able by the user for each interface provided on the baseboard, depending on the data path width of the iSBX board that is installed.

The 16/8 bit mode is used when a 16-bit baseboard must interface with an 8-bit iSBX board. The chip select lines serve the same function as in an 8-bit baseboard with different I/O address assignments. The 16-bit baseboard uses the lower data byte (MD7 to MDO) of the 16-bit word to communicate with the Multimodule board. The upper data byte (MD 15 to MD8) is not defined and should not be used. Only even I/O port addresses are used (Table 4-1). This requires the baseboard to reserve 32 I/O port addresses. The 16 even ports are used, leaving the 16 odd ports unused.

The 16/16 bit mode is used when a 16-bit baseboard must interface with a 16-bit iSBX Multimodule board. The baseboard uses all 16 data lines to com-municate with the iSBX Multimodule board. In this mode, the chip select terms are also used to control low-byte, high-byte, and word transfers as well as address decoding. The MCSO* is used for low-byte (even-byte) transfers;

132 THE MUL TIBUS FAMILY OF BUS STRUCTURES

FIGURE 4-6 iSBX baseboard chip select assignments.

MCS1* is used for high-byte (odd-byte) transfers; and both MCSO* and MCS1*

are used for even word data transfers.

Figure 4-7 shows a portion of the logic equations and possible circuit for part of MCS1 * and MCSO* generation in a 16-bit baseboard system. In this example, the baseboard has Intel's iAPX² 80286 16-bit advanced microprocessor. The baseboard logic generates four signals which are used to generate the two iSBX chip selects. The chip select 1 * and chip select 2* signals indicate that the base-board is addressing an I/O address in the range of OCOH to OCFH (hexadeci-mal) and OBOH to OBFH, respectively. Address 0* is the least significant address bit. When active, it indicates that an even-byte transfer is requested. An active BHEN* (byte high enable) indicates an odd-byte transfer is being requested.

In the 16/8 bit mode the MCS1* and MCS2* terms are simply the chip select 1 * and chip select 2* terms, respectively, without modification and have no data flow control terms in them. In the 16/16 bit mode the MCS1* and MCS2* terms include data flow control. The MCSO* term includes the address 0 term which controls the lower byte (the even byte). Thus, chip select 0* is logically ANDed 2iAPX is a trademark of Intel Corporation, Santa Clara, California.

with address 0* to produce MCSO*. The MCS1* term includes the high-byte control (odd-byte) term BHEN*. Thus, chip select 0* is logically ANDed with BHEN* to produce MCS1*. If the baseboard addresses I/O address OC3H, then chip select 0* will be active and the address odd (address 0* is active). This will result in an active MCS1 *.