A Conceptually Simple Structure

A system bus structure must be easy to learn and use, and at the same time it must be flexible in order to support a wide range of applications. Documenta-tion is a very important aspect of "easy to use"; it must be well structured to help the user understand the bus system. It must be broken down to give the user a step-by-step building-block approach to learning the system bus struc-ture. Application examples of how to use the bus also are very helpful. They can give the user practical experience with the bus structure without having to actually build a prototype. An experienced board designer should be able to understand a new structure in a few hours and design a simple board within a few days after reading the bus specifications.

The Multibus system bus is an asynchronous parallel bus which can be divided into five signal categories: a 24-line address bus, a 16-line bidirectional data bus, eight multilevel interrupt lines, control and timing lines, and power distribution lines. The system bus operates on a master-slave principle. Figure 1-8 shows a typical bus master and some typical bus slaves. The bus master controls the system bus and starts all operations. Bus slaves respond to com-mands put on the system bus by the bus master. The bus master is interlocked to the bus slave module in that the bus master first issues a command and then must wait for an acknowledgment from the receiving bus slave module before continuing. This interlocking mechanism permits bus slave modules of different speeds· to be on the same system bus, since each individual bus slave controls the amount of time it waits before responding with the acknowledgment.

The iSBX concept allows the designer to inexpensively customize standard cost-effective Multibus-compatible boards (or any other board) with particular I/O features. This is done with small (2.85 X 3.7 in; 7.24 X 9.4 cm) I/O mod-ules called iSBX Multimodule boards. They are specialized I/O boards which plug piggyback style onto a variety of baseboards (Fig. 1-9) and thereby provide very low cost local I/O functional expansion. The concept is optimized around VLSI technology and small increments of I/O expansion. The iSBX boards are connected to the baseboard's local bus via the iSBX bus interface, and they con-vert the iSBX bus signals to a defined I/O function. The iSBX Multimodule boards enable the user to configure exactly the capabilities required for the sys-tem, which keeps both system size and cost at minimum levels. Since the I/O expansion is local, no system bus bandwidth is required.

By providing a standard high-speed, tightly coupled connection between the microprocessor and its memory on another board, the iLBX bus permits the expansion of an SBC's local memory in a modular manner (without using the Multibus system bus) beyond what can fit on an SBC. The iLBX bus is

opti-MICROPROCESSOR

_I B

EJ

EJ

MEMORY

I I

I

BUS LOGIC

ADDRESS AND DATA

COMMANDS

ACKNOWLEDGE

FIGURE 1-8 Multibus master and slave diagram.

16 THE MULTI BUS FAMILY OF BUS STRUCTURES

FIGURE 1-9 The iSBX Multimodule board concept.

mized for high-speed memory access. It supports two types of data transfer: a noninterlocked mode for maximum performance and an interlocked mode to support slower memory modules. The bus structure is built upon the master-slave principle, whereby the bus master (the SBC) places address and com-mands on the bus and the slave board (the memory module) decodes and acts on the command. This private bus between the microprocessor and the memory frees the Multibus system bus for DMA or other bus master traffic. Figure 1-10 is a block diagram of an SBC and a memory board connected via the iLBX bus.

The Multichannel bus provides a standard high-speed (8M bytes per second) block-oriented gateway into and out of a Multibus-based system. By utilizing a standard interface, the bus allows multiple heterogeneous devices such as dif-ferent high-speed I/O and memory modules to be connected together. Figure 1-11 is a simplified block diagram of a Multichannel system. The bus structure is an asynchronous parallel bus built upon the master-slave principle with inter-locked 8- and 16-bit data transfers. The Multichannel bus has the ability to link together up to 16 devices that are distributed over a distance of up to 50 ft (15 m) via a twisted pair flat ribbon cable. It has addressing capability of up to 16M bytes of memory and 16M bytes of I/O space on each bus device. Figure 1-12 shows Inters iSBC 589, a high-speed intelligent DMA controller, which connects the Multibus system bus to the Multichannel bus. The 60-pin connector on the top of the board is the Multichannel bus connector.

Another important feature of both the Multibus structure and the

Multi-channel bus is the ability to put multiple master modules on the same bus for multiprocessing configurations. A method is defined to transfer control of the bus between master modules, and it guarantees that only one bus master con-trols the bus at a given time. Both buses also support priority interrupts. This capability permits bus modules to request interruption of normal activity and have a special event serviced by the master microprocessor.

SBC

MULTIBUS SYSTEM BUS

FIGURE 1-10 The iLBX memory expansion bus concept .

...--_ _ A..:.,D.:...DR,.;;;E..:.,SS / DATA (16)

I

DEVICE 1

DEVICE 2

DEVICE 15

FIGURE 1-11 The Multichannel bus block diagram.

MEMORY

DUAL-PORT MEMORY

DEVICE 16

18 THE MULTIBUS FAMILY OF BUS STRUCTURES

FIGURE 1-12 Multibus board with a multichannel interface.

1.2.3 A Structure That Can Incorporate New VLSI Quickly