Command Lines

The iLBX bus has three command lines to control the transfer data cycle. Two signals, address strobe and data strobe, are driven by the master to initiate and control the cycle. Acknowledge, which is driven by the slave, acknowledges and terminates the cycle. These signals are defined in the following section.

ADDRESS STROBE

Address strobe (ASTB*) is an active-low signal driven by the master to initiate a transfer cycle and to inform the slave that valid address and control status are on the bus lines. Since address and status do not remain valid for the entire transfer cycle, the slaves also use the falling edge of ASTB* to latch the address and control status information.

Figure 5-4 shows the timing relations for an iLBX bus transfer cycle.

1. The master places the address and control status on the bus.

2. After meeting the specified setup time for address and control status, the master drives the ASTB* signal low. Upon receiving the active ASTB* signal, the slave, if it is the selected slave, latches the information and begins the cycle. If a slave is not selected, it will wait for the next ASTB*, which signals the start of a new cycle.

DATA STROBE

Data strobe (DSTB*) is an active-low line driven by the master to set up the actual transfer of data. The signal is also used by the master to indicate the end of the transfer cycle. The DSTB* signal, when used in conjunction with the R/W signal, indicates the direction of data flow to the slave. The definition of DSTB* varies slightly depending on the direction of the data transfer from mas-ter to slave (write) or from slave to masmas-ter (read).

During a write operation the master informs the slave that valid data will be on the bus by driving the DSTB* signal low. Figure 5-4 is an example of a write operation. In this figure the active bus master places address and control status information on the bus in the manner described for the address strobe operation above.

3. To inform the slave that the cycle is a write cycle, the master places the R/W control status line into the write mode prior to issuing the ASTB*

signal.

4. After meeting the required setup and hold times for the address, the active master indicates that valid data will be on the bus by driving the DSTB*

line low.

5. The master then drives valid data on the data lines a specified time after it drives DSTB* low. The selected slave samples the data after detecting the falling edge of the DSTB* signal and waiting the specified setup time.

During the read operation the master informs the slave that it can place data on the data bus by driving the DSTB* signal low. A read operation is shown in Fig. 5-5. In a read operation the master places address and control status on the bus in a manner similar to that of the write operation. The main difference is that the R/W status signal now indicates a read cycle to the slave.

3. To inform the slave that the cycle is a read cycle, the master places the R/W control status line into the read mode prior to issuing the ASTB* signal.

4. After the master has met the specified setup and hold times, the master drives the DSTB* signal low.

5. The slave then drives the bus with its data.

180 THE MULTIBUS FAMILY OF BUS STRUCTURES

AB23-ABO ~'I~~~~~ ________ ~~~~~ ______ ~ ________ J~~~

ASTB*

DSTB*

ACK*

FIGURE 5-5 Read data transfer cycle.

ACKNOWLEDGE

The selected slave drives the acknowledge (ACK*) signal to inform the master that the current cycle can be completed. The ACK* signal timing requirements can vary with different master-slave combinations.

There are three basic acknowledge types: (1) acknowledge before data strobe, (2) acknowledge after data strobe, but prior to data valid or accepted, and (3) acknowledge after data strobe and when data is valid or accepted.

Acknowledge types 1 and 2 are called advanced acknowledge in that the slave issues the ACK* signal before the slave accepts data or places valid data on the bus. This type of acknowledge takes advantage of a microprocessor's delay from the time of receiving acknowledge to the time of sampling or removing data.

The first type of acknowledge requires a very tight timing relationship between the master and the slave. The second type of acknowledge relaxes some of the restrictions placed on the first type. The third type of acknowledge does not place any special timing restrictions on the master or the slave. The third type of acknowledge is equivalent to the Multibus system bus XACK * signal.

Since the iLBX bus is an execution bus, it allows for flexible acknowledge timing to gain increases in performance. Although the restrictions decrease through the three types of acknowledge, so does the performance. Type 1 acknowledge offers the best and type 3 the lowest system performance. A type 1 'acknowledge requires a trade-off of a narrow range of compatible boards and a more difficult design for increased performance. The type 1 acknowledge is inflexible with regard to slaves with varying memory speeds or changes in microprocessor clock frequency. The type 3 acknowledge provides the full range of board compatibility for simple system upgrade and a simple design with relaxed timing constraints, rather than optimum performance.

Figures 5-4 and 5-5 show basic acknowledge sequences for write and read

operations, respectively. In these figures the slave is using the type 2 acknowledge.

4. After the master has completed the address portion of the transfer cycle, it issues a DSTB* to the bus.

5. In doing so, it drives data on the data lines.

6. The slave, upon receiving the DSTB* signal, generates the ACK* signal to the master.

7. After receiving the ACK* signal, the master removes the data and the DSTB* signal, which signals the end of the cycle.

Since this is a type 2 acknowledge, the slave must ensure that its acknowledge timing relative to the DSTB* strobe meets the timing requirements of the mas-ter. Specifically, the slave must ensure that, when it issues the ACK* signal, the master will continue to hold data valid on a write so that the slave can complete the cycle. During a read cycle the slave's acknowledge timing must meet the master's timing requirement for input data. If the acknowledge sequence were a type 3, the slave would assert the ACK* signal only when data was valid on a read cycle and was accepted on a write cycle. Early type 1 and 2 acknowl-edges allow for overlap in the data synchronization times of master and slaves.

The penalty for the early acknowledge is the requirement that a user, during system design and integration, understand and modify the master-slave timing relationship.

To optimize system performance, a slave device should provide a means of varying its acknowledge timing to match the master timing. In a primary- and secondary-master system the type 1 and type 2 advanced acknowledge timing must satisfy both master timing requirements. Acknowledge timing during read and write cycles with multiple masters is covered in Chap. 9.