Bus Arbitration and Exchange

As microprocessor costs continue to decrease, it has become economically fea-sible to use multiple microprocessors to meet system performance requirements.

Multiple microprocessors must be able to share global resources. The Multibus system bus supports multiple bus masters (microprocessors) with a hardware arbitration and exchange scheme. Two basic types of bus arbitation methods, serial and parallel, are supported. One method of bus exchange also is sup-ported. All bus arbitration and exchanges are made in synchrony with the bus clock (BCLK *). The bus arbitation and exchange lines can be broken down into three groups:

Class Signal Function

Control BUSY* Busy

BCLK* Bus clock

Bus request BREQ* Bus request

CBRQ* Common bus request Bus priority BPRN* Bus priority in

BPRO* Bus priority out

BUS BUSY

Bus busy (BUSY *) indicates the state of the. bus; it is supplied to all bus modules.

The inactive state means the bus is not being used. All bus masters monitor and can drive the BUSY

*

signal. The controlling bus master uses BUSY

*

to indicate

to the other bus masters that the bus is in use by driving BUSY * in the active state. A requesting bus master must wait until it has priority and the bus is not being used (BUSY* inactive) before it can gain control of the system bus.

BUS CLOCK

Bus clock (BCLK *) is the bus exchange logic master clock; all bus exchanges are in synchrony with it. BCLK* is bused to all bus modules and can be slowed, stopped, or single-stepped. Single-stepping is very useful during the debug phase of a project. The bus clock frequency is very important in determining the speed of a bus control transfer (bus exchange). The number of masters sup-ported by the serial-priority arbitration method (discussed later in this section) is a function of the BCLK* frequency. BCLK* normally operates at about 10 MHz.

BUS PRIORITY IN

Bus priority in (BRPN *) is used to indicate to a particular bus master that, of all current bus requests, it has the highest-priority request for the system bus.

BPRN * also indicates that the master can take control as soon as the system bus is not busy. BPRN* is not bused, and its connection is based on the arbitration method used.

BUS PRIORITY OUT

Bus priority out (BPRO*) is used in a serial or daisy chain bus arbitration scheme (Fig. 2-16) to pass the bus priority along. It is not bused. The BPRN*

of the highest-priorty master is always active (low, or tied to ground); its BPRO*

is connected to the BPRN* input of the master with the next-lower priority.

This, in turn, can be repeated. If the highest-priority master does not need the system bus, it will activate its BPRO* and pass the system bus priority to the next-lower-priority master. This causes the BPRN* of the next bus master to become active, which indicates that it now has the highest priority. If it does not need the system bus, it passes the priority on. A master making a system bus request simply causes its BPRO* to become inactive. That, in turn, causes the next-lower-priority master to lose its bus priority because its l3PRN* has become inactive. It then causes its BPRO* to become inactive because it has lost its priority.

The biggest advantage of a bus arbitration scheme using a daisy chain system is its simplicity. Very few control lines are required, and the number of lines is independent of the number of devices. More devices can be added simply by connecting them to the system bus, provided the AC timings are met.

The biggest disadvantage of the daisy chain scheme is its susceptibility to failure. A failure that occurred in the arbitration circuitry of a device could prevent succeeding devices from ever getting control of the system bus or allow

52 THE MUL TIBUS FAMILY OF BUS STRUCTURES

FIGURE 2-16 Serial-priority bus arbitration:

<D

Master 1 done with the bus. ® Master 1 requests the bus. involved is very simple, and a redundant circuit would increase its reliability.

Another disadvantage is that the priority structure is fixed. The devices farthest from the highest-priority master could be locked out by higher-priority masters if they had a high demand for the system bus.

The maximum number of bus masters in a system is determined by gate delays through the daisy chain logic, which must be less than one BCLK*

period. Figure 2-16 also shows the timing associated with a serial arbitration scheme. A bus arbitration operation can be made each BCLK * cycle (falling edge to falling edge). This requires that all priorities be passed in one bus clock period. The maximum number of bus masters is determined by dividing the amount of time it takes a bus master to pass through the bus priority by the bus clock period. For example, if the bus clock period is 100 ns and a serial pass through delay is 30 ns, the number of masters that can be supported by a serial arbitration method is three (with 10 ns of margin). A more detailed look at serial-priority bus arbitration is taken in Sec. 2.4.

BUS REQUEST

A bus request (BREQ*) is used by a bus master which does not have control of the system bus and wants it. The signal is used only in a parallel arbitration

method (Fig. 2-17). Each bus master has a separate pair of bus request (BREQ*) and bus granted (BPRN *) lines which are used for communicating with the central parallel bus priority resolution circuitry (CPR). A BREQ* and BPRN*

pair of signals need not be assigned a fixed priority. When a bus master requires use of the system bus, it sends a request to the CPR circuitry. The circuitry selects the next bus master to receive the bus grant and notifies the bus master

HIGHEST- PRIORITY

FIGURE 2-17 Parallel-priority bus arbitration:

<D

Master 3 requests the bus. ® Mas-ter 2 requests bus and takes priority away from masMas-ter 3. ® Master 2 done with bus and master 3 regains bus priority.

54 THE MUL TIBUS FAMILY OF BUS STRUCTURES

by activating the appropriate BPRN* signal. Up to 16 bus masters can be sup-ported by using this method.

The overhead time required for bus allocation can be shorter than for a daisy chain scheme, since all the bus requests are presented to the CPR circuitry simultaneously. The bus priority can also be dynamically assigned by using a different method such as fixed, adaptive priority, or round robin. The major disadvantage of the parallel-priority method is the additional circuitry of the CPR module.

COMMON-BUS REQUEST

A common-bus request (CBRQ*) indicates to the bus master in control that no other masters are requesting the bus. This allows the bus master to retain control of the bus without contention during each bus cycle and permits it to execute faster because the bus exchange overhead for each cycle is eliminated. A request for control of the bus by another bus master would activate CBRQ*, which would inform the current master to relinquish control of the bus.

MASTER 1

FIGURE 2·18 Bus exchange flow diagram.

MASTER 3

ARBITRATION I

FIGURE 2-19 Bus arbitration and exchange timing diagram.

Dans le document Guidebook Mu tibus Design (Page 67-72)