The Multibus System Bus
2.3 BUS SIGNAL DEFINITIONS AND OPERATION OVERVIEW
2.3.2 Control Lines
The control lines define the data transfer protocol on the system bus. They can be broken down into four basic groups.
Class
MUTUAL EXCLUSION
Mutual exclusion (LOCK *) is used by a bus master to guarantee that no other bus device or microprocessor can access a resource until that bus master has finished using it. In systems with multiple microprocessors, there must be an established method for the microprocessors to communicate with one another.
One very popular method is through the use of shared memory (RAM). It
8-BIT MASTER 16- BIT MEMORY
BYTE DATO * -DAT7 *
CD CD
EVEN- BYTEBUFFER BUFFER
CD
SWAP- BYTE-BUFFER 16 - BIT MASTER
EVEN-BYTE
CD
BUFFER
ODD-BYTE BUFFER
~ SWAP-BYTE BUFFER
ODD-BYTE BUFFER
DAT8*-DATF*
TRANSFER DATA BHEN * ADRO *
TYPE TRANSFER
CD
8- BIT EVEN ADDRESS HIGH HIGHCD
8-BIT ODD ADDRESS HIGH LOWCD
16 - BIT EVEN ADDRESS LOW HIGHFIGURE 2-9 Data flow on MuItibus data lines.
40 THE MUL TlBUS FAMILY OF BUS STRUCTURES
requires no special mechanisms between the microprocessors-they communi-cate by passing messages stored in the RAM. The message is guarded by a flag (a byte in the RAM) which indicates if there is a valid message. When this
BUS MASTER
LOCK·
MULTIBUS SYSTEM BUS
TIMING
MRDC·
---,L __________
L ~~----~ L...-_ _ _ -.l1r---LOCK. - - - , I~. ____________________________________ ~I
r---LFREEZE
l
RELEASEDUAL-PORT CONTROLLER DUAL-PORT CONTROLLER
BUS MASTER
INITIATE FIRST CYCLE PRESENT ADDRESS DRIVE READ COMMAND LOW
I
•
TERMINATE FIRST CYCLE
DUAL-PORT CONTROLLER
RESPOND TO BUS MASTER +
WAIT FOR READ COMMAND LOW IF ADDRESSED LOCATION IS ON-BOARD THEN ACCESS DATA
DRIVE TRANSFER ACKNOWLEDGE LOW IF LOCK LINE LOW. FREEZE DUAL-PORT
TO RESPOND ONLY TO BUS COMMANDS I
WAIT FOR RESPONSE (TRANSFER ACKNOWLEDGE LOW) STORE DATA
RELEASE READ COMMAND I
FIGURE 2-10 Multibus lock operation.
method is used, there are many cases in which one of the microprocessors must have exclusive access to the flag. While one of the microprocessors is updating the flag, another microprocessor must not be permitted to have access to it. A microprocessor must have the ability to read the flag, test it for validity, and write back into the flag in order to let other microprocessors know that it now owns the flag and corresponding message (without another microprocessor intervening). This operation, called read, modify, and write, provides the microprocessor with exclusive access to or mutual exclusion of a memory loca-tion for both the read and the write operaloca-tions.
The Multibus system bus provides for mutual exclusion between bus masters simply by holding the bus until the operation is completed. The bus master can gain control of the system bus, perform
a
read operation, test the data, and then perform the write operation. The LOCK * line allows this mutual exclusion to be extended off the bus. This signal is required only in multiple-port RAM board designs when the bus master needs to prevent the microprocessor on another module from getting access to its own multiple dual memory (memory with multiple paths into it). Figure 2-10 is an example of how LOCK* is usedCONTINUE TO FREEZE DUAL-PORT TO RESPOND ONLY TO BUS COMMANDS
DRIVE TRANSFER ACKNOWLEDGE LOW , ' ______________________ ~I
RELEASE DUAL-PORT CONTROLLER TO RESPOND TO ON-BOARD REQUESTS
I
42 THE MUL TIBUS FAMILY OF BUS STRUCTURES
in a dual-port design. The bus hybrid locks its dual-port memory to the Multi-bus system Multi-bus when it is addressed and the LOCK* signal is active. The dual-port logic on the bus module will not permit access to the memory by the local microprocessor until LOCK * is driven inactive.
CONST ANT CLOCK
Constant clock (CCLK*) is a general-purpose clock used by bus modules. The frequency is approximately 10 MHz. The most common use of CCLK* is on bus slave modules for acknowledge generation logic.
INITIALIZE
Initialize (INIT*) is used to put the system in a known state before bus cycles are started. INIT* is typically used at power-up time in order to guarantee that the system starts in the same way each time and also when a major error occurs and the only recovery is a complete system restart. All bus masters should both receive and drive the INIT* signal. This causes the entire system to start at the same time, because the INIT* signal will not become inactive until the slowest board reset is completed.
COMMAND LINES
The command lines (MWTC*, MRDC*, 10WC*, 10RC*) are controlled by the bus master and are used to request an operation of a bus slave device. _There are four commands: memory read and write and I/O read and write. Each has a unique signal on the bus. The four commands are used to support two types of operations: memory and I/O. Microprocessors such as the 8085 have instruc-tions dedicated to I/O operainstruc-tions; that is, there are specific output and input instructions. These instructions initiate special machine cycles which cause information to flow between the microprocessor and an I/O port location.
An active command indicates to the bus slave that the address lines are valid and that the bus slave should perform the specified operation. Only one of the four commands can be active at a time. A read command is used by the bus master to request that data be sent from the bus slav,~. Conversely, a write com-mand is used by the bus master to send data to the bus slave.
TRANSFER ACKNOWLEDGE
Transfer acknowledge (XACK*) is used by the bus slave to inform the current bus master that the requested operation is complete. For a memory write cycle, an active XACK * indicates (to the bus master) that the data on the data lines is now stored in the memory location specified on the address lines. For an I/O read cycle, it means that the data on the data lines from the addressed I/O device is valid. This signal permits the bus master to proceed to the completion of the bus cycle.
The bus master command and bus slave transfer acknowledge relationship provides the interlocking mechanism which permits modules of different speeds to be on the system bus. The bus master initiates the bus data transfer and then waits for the bus slave to inform it when the operation is completed via the transfer acknowledge (XACK*) signal. Thus, if there are two bus slaves, one that can transfer data at a 1M byte per second rate and another that can transfer data at a 2M bytes per second rate, both can operate at maximum rate. This also permits a module to be replaced with a faster or slower module without modification of the bus masters.
If a bus slave fails to generate an XACK*, the bus master will not be able to complete the bus cycle. Since the bus master continues to wait, the system will stop. This situation will occur only if the bus master tries to access a resource that was not present on the system bus. One way to prevent the stoppage is to provide a time-out function which will terminate the bus cycle, after some fixed period of time, by generating XACK*. This capability is used in systems with different amounts of RAM when the system software needs to find out how much memory is available. The software starts at the beginning of RAM and does a test on that location. If the RAM can be written into and that same data read back, the location is in the system. The software continues through mem-ory until it finds a bad location which it interprets as being top of memmem-ory. The time-out function is a separate piece of logic which typically is on all bus masters.