Control Lines

The control lines define the data transfer protocol on the iSBX bus. The control lines can be broken down into four basic groups.

Class Signal Function

Commands 10RD* I/O read command 10WRT* I/O write command System control MWAIT* Extend command until done

MPST* iSBX board present

DMA MDRQT DMA request

MDACK* DMA acknowledge TDMA Terminate DMA

Utilities MCLK iSBX clock

RESET Initialize

COMMAND LINES

The command lines IORD* and IOWRT* are negative true signals controlled by the baseboard and are inputs used to request an operation of an iSBX

Mul-..

TYPE

CD

CD

®

o

®

8- BIT EVEN ADDRESS

8- BIT ODD ADDRESS

16-BIT EVEN ADDRESS

8-BIT EVEN ADDRESS

8-BIT ODD ADDRESS

16-BIT

16- BIT

16-BIT

8-BIT

8-BIT

FIGURE 4-8 Data transfer types.

LOCAL DATA BUS ON-BOARD BUFFERS iSBX BUS I MULTIMODULE EVEN BYTES h:::::::::::::::::::}}}}:)):}}! EVEN- BYTE BUFFER _ MD7 -MOO

ODD BYTES ODD-BYTE BUFFER

r=:>

EVEN BYTES EVEN-BYTE BUFFER

r=:>

1000 BYTES W()ft}}})}}}}};:1 O-DD-BYTE BUFFER

r):\::::::;:;4>

EVEN BYTES 1:::::)::)))::)::t)):}:::)::1 EVEN-BYTE BUFFER _ MD7-MDO

ODD BYTES I}:::::):}::}::::}::}::::::::::}r! ODD-BYTE BUFFER _ MDI5-MD8

BUFFER MD7-MDO

BUFFER MD7-MDO

8-BIT OR 16-BIT

16-BIT

16-BIT

8-BIT

8-BIT

136 THE MUL TIBUS FAMIL V OF BUS STRUCTURES

EVEN-

CD®

EVEN-BYTE MD7-MDO BYTE

BUFFER PORT

000-

000-BYTE MDIS-MD8 BYTE

BUFFER

00

iSBX

IS-BIT MULTIMODULE

BASEBOARD BOARD

TRANSFER TYPE DATA TRANSFER MCSO* MCSI*

CD

0

0

FIGURE 4-9 iSBX bus data flow control (16/16 and 16/8 bit modes).

timodule board. There are two commands, each with its unique signal on the bus. An active command indicates to the iSBX board that the address and chip select lines are valid and that the selected (MCS* active) iSBX Multimodule board should perform the specified operation. The I/O read command is used by the baseboard to request that data be sent from the iSBX Multimodule I/O port to the baseboard. Conversely, an I/O write command is used by the base-board to send data from the basebase-board to the iSBX Multimodule I/O port.

MUL TIMODULE WAIT

Multimodule wait (MW AlT.) is a negative true signal used by the iSBX Mul-timodule board to extend the current data transfer cycle. The extension is accomplished by putting the microprocessor on the baseboard in a wait state and thereby providing additional time for the iSBX Multimodule board to per-form the requested operation. The MW AlT. signal is generated by the iSBX Multimodule board from address and chip select information only. When the iSBX Multimodule has completed the requested operation, it drives MW AlT.

inactive. This permits the microprocessor on the baseboard to continue. The interlocking mechanism permits iSBX Multimodule boards of different speeds to be on the bus. The interlocked command protocol can be summarized as follows: First the baseboard generates valid address and chip select(s); then the iSBX Multimodule board can cause the baseboard to wait-extend its current

data cycle by activating MW AIT*. The iSBX Multimodule board controls the amount of time that it needs to wait. After it has waited long enough to perform the requested operation, it responds with an inactive MW AIT*, which permits the baseboard to continue.

The iSBX bus uses a negative type of acknowledgment method. It assumes that all operations will occur at the baseboard's maximum speed unless told to wait. The baseboard starts an operation, and it is the responsibility of the iSBX Multimodule board to tell the baseboard to wait if more time is needed to per-form the operation. The MW AIT* signal is normally in the no-wait condition, which permits the baseboard to continue at maximum speed. The advantages of a negative type of acknowledgment method are low overhead and no special circuitry for time-out (the state when a nonexistent location is accessed). A pos-itive acknowledgment method, which is used on Multibus systems, requires the bus slave module to generate a response before continuing. The advantages of a positive acknowledgment method are the independent timings of the master and the slave of two communicating units. The slave unit is not required to generate a wait signal in a fixed amount of time, and future baseboards with faster microprocessors will not need added extra circuitry to guarantee the wait timing.

MUL TIMODULE PRESENT

Multimodule present (MPST*) is a negative true signal driven low by an iSBX Multimodule board to inform the baseboard that an iSBX board is installed. This interface signal goes to the baseboard decode logic. If the Multimodule is not installed, the address space normally reserved for the Multimodule board I/O ports can be used on system bus slave boards. This is important when designing a new board with the iSBX interface that also has to be backward-compatible with an older product. When the MPST* signal is in the inactive state, the iSBX I/O port locations will be decoded to be off board (not present on the board) and the SBC will go to the system bus to find them; it will appear as if there were no iSBX interface on the SBG If the Multimodule is installed, then the I/O decode logic is activated to respond to the iSBX I/O port addresses as on-board resources and route the requests to the Multimodule I/O port. This signal is not needed for new products, since the iSBX addresses will be reserved for future expansion anyway.