TECHNICAL INFORMATION

HP 13255 ROM (EA) MODULE

Manual Part No. 13255-91111 PRINTED

AUG-01-76

DATA TERMINAL

TECHNICAL INFORMATION

HEWLETTi:j PACKARD

Printed in U.S.A.

13255

ROM (t.A) Module

1.0 INTRODUCTION.

13255-91111/02 Rev AUG-01-76

The ~OM (EA) Module contains space for up to 12K Of ROM for storing the operating system firmware.

2.0 OPERATING PARAMETERS.

A summary of operating parameters for the ROM (EA) Module is contained In tables 1.0 through 5.0.

Table 1.0 Physical Parameters

===-=================================================.===========================

part

Number Nomenclature

============= ===========:=c===========:====

02640-60150 ROM (EA) PCA

Size (L x W x D) +1-0.100 Inches

=======================

12.5 x ^4.0 x ^0.5

Weight I (Pounds) I

_

---_

- ---_

_

-

0.44

======================================================================'========

Number of Backplane Slots Required: 1

======z================z=================:=====================:================

HP 13255 POM (EA) MODULE

Manual Part No. 13255-91111 PRINTED

AUG-01-76

NOTICE

'rhe information contained in this document is subject to change '-i thout notice.

H~WLETT-PACKAHD MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL, .. INCLUDING, BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Hewlett-Packard :Shall not be liable for errors contained herein or for incidental or consequential damages In connection with the furnishing, performance, or use of this material.

'rhls document contains proprietary information which is protected by

copyright. All rights are reserved. No part of this document may be Photocopied or reproduced without the prior written consent of Hewlett- Packard Company.

----~-,----~---~----~--- ---Copyright c 1976 by HEWLETT-PACKARD COMPANY

NOTE: This document is part of the 264XX DATA TERMINAL product series Technical Information Package (HP 13255).

13255

ROM (t.A) Module

1.0 INTRODUCTION.

13255-91111/02 Rev AUG-Ol-76

The ROM (EA) Module contains space for up to 12K Of ROM for storing the operating system firmware.

2.0 OPERATING PARAMETERS.

A summary of operating parameters for the ROM (EA) Module is contained in tables 1.0 through 5.0.

Table 1.0 Physical Parameters

=====================================================.===========================

Size (L

x

x

Nomenclature +1-0.100 Inches

========z:==== =============================: =======================

02640-60150 ROM (EA) peA 12.5

x

x

Weight I (Pounds) I

- ^{... - ...}

-...

-_

_

---

0.44

==================================z====z=============================='========

Number of Baekplane Slots Required: 1

=====:z==================================:===================:==================

13255

ROM (EA) Module

13255-91111/03 Rev AUG-Ol-76

Table 2.0 Reliability and Environmental Information

================================================================================

I:.nvironmental: ( X ) HP Class B ⁽ ) Othe'r:

Restrictions: Type tested at product level

===========:===================================================================

Failure Rate: 1.169 (percent per 1000 hours)

================================================================================

Table 3.0 Power Supply and Clock Requirements - Measured (At +1-5\ Unless Otnerwise Specified)

================================================================================

+5 Volt Supply

, 200 mA

(with 6 ROMs loaded)

+12 Volt Supply

€I rnA

NOT APPLICABLE

-12 Volt Supply

~ 150 mA (With 6 ROMS

loaded)

-42 Volt Supply

€I rnA

NOT APPLICABLE

====================================== =======================================

115 volts ac 220 volts ac

A A

NOT APPLICABLE NOT APPLICABLE

==============================================================================

CloCk Frequency: 4.915 MHz +1-0.1%

================================================================================

13255

ROM (EA) Module

Table 4.0 Jumper Definitions

13255-91111/04 Rev AUG-OI-76

========:===================z=========================:::::==::=::z:==::=::=:=::

peA Designation

================

START ADDR

ROM

EN AtjLi:,

ROM

16K 32K 1_-

0- 2- 4-

2 4 6 6- 8 8-10 10-12 1_-

Function

---

===============:============== ==============================

If all START ADDRESS Jumpers are IN, then

START ADDR=O Add 0 to START ADDR Add 0 to START ADDR

0- 21< ROM Enabled 2- 41< ROM Enabled 4- ^6K ROM ~:nabled

6- 8f( ROM Enabled 8-10K ROM Enabled 10-12K ROM Enabled

Add 16K to START ADDR Add 32K to START ADDR

0- 21< ROM Disabled 2- 4K ROM DIsabled 4- ^6K ROM Disabled 6- 8K ROM nisabled 8-10K ROM DIsabled 10-12K ^ROM Disabled

=======:========================================================================

13255

RUM (Jt::A) Module

5.0 Connector Information

1325~-91111/05

Rev AUG-01-76

=====:===============================:===========================================

C1onnector anld Pin ^NO.

====:==========

Pi, Pin '1

-:2

-,3

·,4 -5 -6 -7 -8

-9 -10 -11 -12 -13 -14 -15 -16 -17 -18 -19 -20 -21 -22

Signal Name

+5V GND

SYS eLK -l2V ADORO ADORl ADOR2 AOOR3 ADOR4 ADOR5 ADDR6 ADDR7 ADDR8 ADOR9 AODRI0 ADDRll ADDR12 ADDR13 ADOf<14 ADOR15

1/0

GNO

Signal Description

==:==============:=============~==============

+5 Volt Power Supply

Ground Common Return (Power and Signal) 4.915 MHz System Clock

-12 Volt Power Supply

Negative True, Address Bit 0 Negative True, Address Bit ¹ Negative True, Address Bit 2 Negative True, Address Bit 3 Negative True, Address Bit 4 Negative True, Address Bit 5 Negative True, Address Bit 6 Negative True, Address Bit ⁷ Negative True, Address Bit 8 Negative True, Address Bit 9 Negative True, Address Bit 10 Negative True, Address Bit ¹¹ Negative True, Address Bit 12 Negative True, Adaress Bit 13 Negative True, Address Bit 14 Negative True, Address Rit 15

Negative True, Input Output/Memory Ground Common Return (power and Signal)

=========================================================:======================

13255

ROM ^(t;A) Module

Table 5.0 Connector Information (Cont'd.)

13255-91111/06 Fev AUG-Ol-76

=======:========================================================================

connector I ana Pin ^NO. I

==:===========

PI, Pin A -8 -C -0 -E -F -H -J -K -L -M -N -p -R -8 -T

-u -v -w -x

-y

-z

Signal Name

=======::========

GND

BUSO BUS1

BUS2

BUS3 BUS4

BUS5 8USb

BUS1 wRITE

WAIT PRIOR IN PRIOR OUT

REO

Signal Descrt.ptlon

========;=====================================

Ground Common Return (Power and 51gnal)

} }

} Not used

,

}

Negative True, Data Bus Bit 0

Negative True, Data Bus Bit 1 Negative True, Data Bus Bit 2

Negative True, Data Bus Bit 3 Negative True, Data Bus Bit ⁴ Negative True, Data Bus Bit 5 Negative True, Data Bus Bit 6 Negative True, Data Bus Bit 1

Negative True, Write/Read Type Cycle Not used

Negative 'frue, wait Control Line Bus Controller Priority In

Bus Controller Priority Out

} )

} Not used

) }

Negative True, Request (Bus Data Currently Valid)

Not used

=========================================:a===================================_:

13255

ROM (EA) Module

13255-91111/07 Rev AUG-01-16

3.0 FUNCTIONAL DESCRIPTION. Refer to the block diagram (figure 1), schematic diagram (figure 2), timing diagram (figure 3), component location diagram (figure 4), and parts list (02640-60111) located in the appendix.

The ~OM (EA) Module has the capacity Of storing from 0 to 12K bytes of firmware. As shown on the block diagram, the ROM (EA) Module consists of a ROM block, start decoder, ROM selector and jumpers, timing logic, and an output buffer.

3.1 ROM. The ROM block can contain up to six chips (EA 4900 or equivalent) with eaCh Chip containing 2K bytes. Any combination of chips can be inserted.

3.2 START DECODER. The start d~coder applies a SELECT ENAbLE (U410, Pin 3) to the ROM Selector and Enable Jumpers. This signal is determined oy the confiquration of the START ADDR Jumpers and address bits ADDR14 and ADDR15.

3.3 ROM SELECTOR AND ENABLE JUMPERS. The ROM selector decodes ADDRt1,

~-...-

-

ADDR12, and ADDR13 into six select signals it the SELECT ENABLE, I/O, and WRITE signals are high. In order to propagate the select signals

to the ROM Chips, the proper ROM ENASLE Jumper must be plugged in.

3.4 TIMING LOGIC. If any 2K of ROM is selected and the proper ROM ENABLE Jumper is inserted, then the CLOCK ENABLE (US8, Pin 8) signal is generated and the timing logic is enabled. This results in WAIT and

~EAD AODK signals being generated and a byte from ROM is read. The

13255

ROM (t:A) Module 13255-91111/08

Rev AUG-01-76

signals REQ, I/O, WRITE and ADDR11 through AODR15 generate the CLOCK ENABLE signal that enabl~s tne 93LI059 counter (U48). The counter advances to the states labeled in the timing diagram in figure 3 on the ClOCK edges indicated bY arrows. When REQ is asserted, RF.AD ADDR and wAlT gO low. state 2 of the counter and the positive half of SYS CLK terminate the READ AUOR signal. On the sixth ClOCK, the counter 1s preset to state 8 and WAIT is terminated. By that time ROM data byte (BUSO through BUS7) Is val1d. When REQ is dropped, CLOCK ENABLE is terminated and the output buffer is disabled.

3.5 OUTPUT BUFFER. The ouput buffer enables a RUM byte on the bus when the CLOCK ENABLE signal is generated.

4.0 ROM ORDERING INFORMATION.

4.1 VENDOR. The ^ROM used is Electronic Arrays' EA4900. It is a 16,384 bit static read-only-memory chip organized as 2,048 words, 8 bits per word.

4.2 SPECIFICATION. Refer to Electronic Arrays' EA 4900 specification sheet.

4.3 DATA CARD FORMATTING. Electronic Arrays' requires that the ROM data be supplied on a decK of standard 80-column computer cards. Each card Is to be punched as follows: Note that for the EA4900, a 3-digit octal number is used for representing the 8 ROM outputs for each byte.

13255

ROM (I~A) Module 13255-91111/09

Rev AUG-01-76

Card Column No.

EA 4900 1-4

5-7

8-10

11-13

50-52 69-80

Card Contents

Punch a 4-di9it octal number representing the input address for the first of the 16 output words appearing on this card. (This is the initial address.)

PunCh a 3-di91t octal number representing the outputs for the initial input address.

Punch a 3-diglt octal number representing the outputs for the initial input address +1.

Punch a 3-dlg1t octal number representing the outputs for the initial input address +2.

Punch a 3-di91t octal number representing the outputs for the initial input address +15.

The unique number assigned to this ROM pattern by EA must be punChed in this field enclosed by blank spaces.

This number can be obtained by contacting your local EA salesman, representative, or the marketing depart- ment at the factory directly.

Each card, therefore carries (in octal) the initial input address for the 16 output words contained on that card, the 16 output words

themselves (in octal) and the unique ROM number. The cards must be provided for all pOssible sequential address locations (in blOCKS of 16). A 2048 word ROM, therefore, requires 128 cards, with all 16 output words defined on each card.

4.4 ROM PULL-UPS. The ROM has programmable input resistors. To provide minimum high level Input voltage (3.5V) at least one ROM Chip must be programmed with internal pull-ups.

With regard to the Sinking capability of the address driver (74LS04) onlY four ROM chips can have the internal input resistors.

At>biC 14-, ADt>t< 15 A~bR. 0 -ADC>R. ,0

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Figure 1

ROM (EA) Module BloCk Dlagra.

AUG-01-7& 13255-91111

~ lfo Wiifl

PI-Y I

I PI-:l1 P/-P .~

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TO I~'~

BACKPLANE" ~~

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I BUFFE.R I t

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---.,

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1/ .3 " 3 _ _ -1

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Figure 2

ROM (EA) peA Schematic Diagram

AUG-Ol-76 13255-91111

5IGt-JAL NAME SYS c.L-1(

ADDIC 0-15 1: _~ 10

l

REQ CLOC.k:..

E~A..eL£

k>E" A D A DD~

WAiT

BUS 0 -...,

C.ON~E.c..TOR , PIN t-JUMeE~

Pi, P\N~

Pi I PII\J 5 -2.0

Pi , PIN 'Z I

P'2., PI~ ~

USB, PIN 1l

u~e \ Plt-J <0

Pi, PII\j 5 P1.,PIt.JE-t-J

e~

~

________________

~

1 0

n

~ ______________________ ~~l

____________________________

________ _

C

Figure 3

ROM (EA) Module Timing DIagram

AUG-Ol-76 13255-91111

rr.Il

M ^It) CD

(,,) (,,) (,,)

-

...

a:: _{~ :J} ~ :J ^::)

X ) ( )( X ⁾⁽

-

-

^•

(,,) (.) (,,)

~ ~ ~

~

+ C2 + Cl

" ⁰⁰

(,,) (.)

~ :J X

In CD

[)

-

- G

N (.)

N N

(.)

START ADDRESS

18K

j

_N , R O M i

~~

N.CDoo~~:!~

I I • I I I I •

ON.CD 00 S2~'

U29

< 1IIIIIIIWlI

C19 R2 11

~ ~

R3 11

U48

S ~ ~

C23

~ G

Figure 4

ROM (EA) peA Component Location Diagram

AUG-Ol-76 13255-91111

Replaceable Parts lReference HP Part

Qty Description Mfr

Mfr Part Number

!Designation Number Code

02 tlto-bOll 1 1 '.P. CONTROL STORE ASSEMBLY 281t80 02640-60111 DATE CQDE: A-151t7-22

REVISION DATi: Q8..1:t-7f'

i.l Olto-O~93 1 CAPAC 1 TOR-f XC 39Uf+-101 10VDC TA 56289 15OO396X901082

C., Olto-l71t6 1 CAPACITOR-FXD 15UF+-I01 lOVDC TA 56289 1500156X902082

1.:.) Ol!0-0121 12 UPACIToa-fXD .IUF +80-20% 50"'40C CER 281t80 0150-0121 C," o 1 ~o-0121 CAPAC ITOR-FXD .1Uf +80-201 51lJoIVOC CER 281t80 015.0-0121

(.) 01!0-0121 CAPAC 1 TOR-FXo .1Uf +80-201 50WVDC CEil 281t80 0150-0121

'-'i) ^01!0-0121 CAPAC I Toa-fXO .1UF +80-201 50WVDC CER 281t80 0150-0121

C1 Ol!0-012l CAPACITOR-FXIl .1Uf +80-20l 50WVDC CEa 281t80 0150-0121

("tJ 01!0-0121 CAPAC I TOR-FXO .1UF +80-l01 50WVOC CER 281t80 0150-0121

1.:1.1. 0150-0121 CAPAC ITOR-FXO .1UF +SO-20' 50WVDC CEa 281t80 0150-0121

(,12 01 !0-0121 CAPAC nOR-F xc .IUf +80-20% 50.VOC CEil 281t80 0150-0121

CU 0150-0121 CAPAC I TOR-fXD .IUf +SO-201 50WVOC CER 28ltao 015.0-0121

("H OBo-Ol2l CAPAC ITOR-FXO .1UF +80-l0:& 50.VOC CER 2Slt80 0150-0121

1.:15 01!0-0121 UPACITOR-fXO .IUF +S0-201 50W\lOC CER 2Slt80 0150-0121

C1t. OBo-Ol2l CAPAC ITOR-fXIl .1UF +80-20"' 50WVOC CER 281t80 0150-0121 (;,.1.9 OH0-2055 5 CAPACITOi-FXO .01UF +80-201 100.VOC CER 281t80 0160-2055

C.20 0160-2055 CAPACITOR-fXo .01UF +80-l01 100_VDC CER 281t80 0160-2055

("ll OHo-l055 CAPACITOR-fXD .OIUf +80-201 100WVDC CER 281tSO 0160-2055

c..a 0160-2055 CAPACITOR-FXD .01UF +00-201 10C.VDe tER 281t80 0160-2055

C23 0160-2055 CAPACITOR -FXD .01UF +80-20% 100WVDC CER 28480 0160-2055

EI 03to-012 .. 1 TERMINAL-STUD SGl-PIN PRE SS-MT G 281t80 0360-0121t

IU 1810-0055 1 METWORK-BES 9-PIN-SIP .15-PIN-SPCG 281t80 1810-0055

j(.2 1810-0125 2 NETWORK-RES '-PIN-SIP .125-PIN-SPCG 11236 150

iU 1810-012!j NETWORK-AES 8-PIN-SIP .125-PIN-SPCG 11236 150

U . .:9 1820-1216 1 IC-DIGITAl SN1ltlS138N TTL lS 3 01295 SN1ItlSl38N

U'}'~ IS,,0-1199 3 Ie-DIGITAL SoNHlSOItN Tll lS HEX 1 01295 SN7ItlS04N u·ft£ 18~0-1.209 2 Ie-DIGITAL 5J'jHlS38N TTL lS QUAD 2 NAND 01295 SN7ItLS38N U'.3 1820-1209 IC-DIGITAl SN7ltlS38N TTL loS ~UAD 2 NAND 01295 SN74lS38N

U·.'" lS,,0-1199 Ie-DIGITAL s.NHlSOItN TTL lS HEX 1 01295 SN7ItlSOItN

V ,It !;; 18010-1199 Ie-DIGITAL SIiI71tlSOitN TTL lS HEX 1 01295 SN7ltlSOitN

IJ'H 1820-1191 3 It-DIGITAL SN71tlSOON TTL LS QUAD 2 NAND 01295 SN14lS00N

u·1t8 18,,0-0669 1 IC.-DIGITAl 93110DC TIL l 8eD SYNCHRO 01263 931100C U·ft9 1820-1197 IC-DI GIT Al SH71tlSOON TTL loS QUAD 2 NAND 01295 SN14lSOON

U:)8 18 "o-06tl 1 1 IC-DIGITAl S~7ItSOON TTL SQUAD 2 NAND 01295 SN74S00N

1.1:)9 18~0-1197 ie-DIGITAL SN7ltlSOON TTL lS QUAD 2 NAND 01295 SNlItlSO~

U:HO lS010-1,,0'1 1 IC-DIGITAl SHlltlS30N TTL loS S NAND 01295 SH74LS30N

""HoO lS20-1215 1 IC-DIGITAl SHlltlS136N TTL lS QUAD 2 01295 SN7ItlS136N

,,1 81~9-0005 .2 WIRE .22AWG W PVC 1X,22 SOt 28ltao 8159-0005

12~a-012't 6 PIN-PRQGRAMMING JUMPER;.30 tONTACT 91506 8136-U5G1

.u 81!9-0005 ~IRE 22AWG w PVC lX22 SOC 281t80 8159-0005

XIJ.i1 12Co-051tl 6 SOCKET-IC 2+-CONT DIP DIP-SlDR 281t80 1200-051t1

XlJ2" 12CD-05ltl SOCKET-Ie 24-tONT DIP DIP-SlOR 281t80 1200-05ltl

XlJl3 12Co-05ltl SOCKET-IC 21t-tONT DIP DIP-SlDR 281t80 1200-05U

XIJl't 12Co-05ltl SOCKET-Ie 24-tONT DIP DIP-SlOR 2Slt80 1200-OS41

XtJ.2j 12Co-0541 SOCK£T-Ie 21t-tONT DIP OIP-SlDR 281t80 1200-0541

XUll> 12Co-051tl SOCKET-Ie 21t-tONT DIP DIP-SlOR 281t80 1200-0541

W:l 12Co-Olt82 1 SOCKET-It 16-tONT DIP-SlDR 4)1506 516-AGI10