A/Q-DSA CONTROL

89758600 CONTR..OL DATA CORPORATION

CONTROL DATA®

TTL A/Q-DSA BUS EXPANDER

AT310-A

GENERAL DESCRIPTION

OPERATION AND PROGRAMMING INSTAllATION AND CHECKOUT THEORY OF OPERATION

DIAGRAMS MAINTENANCE PARTS DATA WIRE LISTS

MAINTENANCE AIDS

HARDWARE REFERENCE/

CUSTOMER ENGINEERING MANUAL

REVISION RECORD

REVISION DESCRIPTION

01 Released to Class B, 15 November 1974 ECO CKI026 A Released to Class A bv ECO CK1535. dated 1 July 1976

Publication No, 89758600

© 1974. 1975. 1976

by Control Data Corporation

Printed in the United States of America

ii

Address comments concerning this manual to:

Control Data Corporation

Small Computer Development Division 4455 Eastgate Mall

La Jolla, California 92037

or use Comment Sheet in the back of this manual.

MANUAL TO EQUIPMENT LEVEL CORREI.ATIOf" SHEET

SNUT_I 0'-1. EQUiPMENTS

--

--~----

~At\IlIAl

FfeK~R ^ECO . SERIES SIN LOGIC DIA(

REV

ECO CK762 02 51

01 ECO CK941 03 101 03

1047 03

1072 04

1274 04 333-336

339,345, ^:

A 1535 346 A

.

- -

iii 89758600 A

TABLE OF CONTENTS

SECTION Page

1 GENERAL DESCRIPTION

Introduction _1-1

2 OPERATION AND PROGRAMMING 3 INSTALLATION AND CHECKOUT

Installation _3-1

Unpacking _3-1

Physical Limitations _3-1

Power Requirements _3-1

Cabling and Connectors _3-1

Cooling Requirements _3-2

Environmental Considerations _3-2

Preparation and Installation _3-2

Checkout _3-3

4 THEORY OF OPERATION

Introduction _4-1

General _4-2

Circuit Types _4-3

Propagation Delay _4-6

Fan-In and Fan-Out _4-6

Basic PWA Differences _4-6

Interrupt and Scanner Connections _4-8

Interrupt Connections _4-8

DSA Scanner Connections 4-8

Signal Routing _4-10

A/Q Expansion _4-10

DSA Expansion _4-10

5 LOGIC DIAGRAMS

Key to Logic Symbols _5-1

Signal Flow _5-2

Logic Diagram _5-4

6 MAINTENANCE

Scope _6-1

Tools and Equipment _6-1

Publications _6-1

Maintenance _6-1

7 MAINTENANCE AIDS

8 PARTS DATA

Parts Data _8-1

9 WIRE LIST

Wire Li st _9-1

89758600

A

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TABLES

TABLE Page

1-1 SPECIFICATIONS 1-3

3-1 INTERRUPT POSITIONS 3-7

9-1 EXTERNAL CABLE WIRE LIST 9-2

9-2 PWB PIN LIST 9-10

FIGURES

Figure Page

1-1 BASIC A/Q - DSA EXPANSION CONFIGURATION 1-1

3-1 LOCATIONS OF PWA's IN ENCLOSURE 3-5

3-2 LOCATIONS FOR JUMPER PLUG PLACEMENT 3-6

4-1 EXPANSION THROUGH TWO ENCLOSURES 4-2

4-2 LINE DRIVER CIRCUITS 4-4

4-3 SCANNER CONNECTIONS 4-9

vi 89758600 . A

INTRODUCTION

SECTION 1 GENERAL DESCRIPTION

The CONTROL DATA(8) AT310-A TTL A/Q-DSA Bus Expander consists of two basic 50-Pak TTL type IC logic

assemblies and a flat cable, used in either the A/Q or DSA bus to expand the capabilities of the CPU. The AT310-A may be used with the standard BT148-A Expansion Enclosure or in a special purpose enclosure and the AB107/AB108

cpu.

Up to two expansion enclosures may be connected to the com- puter, each with a set of expanders. When expansion of both the A/Q and DSA buses is required, two sets of ~xpanders must be used.

Figure 1-1 shows the expansion of both the A/Q and DSA buses, using two sets of expanders. The flat cable supplied, is connected to P2 in each enclosure.

A/Q SLOT A/Q SLOT

EXPANOER EXPANDER

PWA PWA

"M" "R"

tONFlGURATION P2 P}-CQN FI GURA TI 0'

I I

ABl07/ABl08 EXPA. .. SION

COMPUTER ENCLOSUR£

DSA SLOT

FLAT CABLE DSA SLOT

EXPANDER ASSY EXPANDER

PWA PWA

"M" "R"

ONFIGURATION P2 P2 CONFIGURATI!»

1"1 r

Figure 1-1. Basic A/Q-DSA Expansion Configuration

89758600 ^'A 1-1

TABLE 1-1. SPECIFICATIONS

Specifications Explanation

PHYSICAL CHARACTERISTICS Dimensions

Width length Depth

ENVIRONMENT Temperature

Shipping Storage Operating Humidity

Shipping Storage Operating POWER

Input Requirements Signal level

Low State (0) High State (l) Ground

89758600 A

613. h 16 lnc es 12 ~ inches

~

-40°F ~o 158°F (-40⁰

e

to 70 C)

14°F to 122°F (lOoe to 50⁰e)

40⁰

b

o

5 Volts dc

0.4 Volts dc, or less 2.4 Volts dc, or more Logic ground is connected

to computer logic ground

1-3

OPERATION AND

PROGRAMMING

89758600 IA,

SECTION 2

OPERATION AND PROGRAMMING

Programming of the AT310-A TTL A/Q-DSA Bus Expander is not required. Refer to the 1784 Computer Reference Manual or to the AB107/AB1OB Computer Customer Engineering Manual and the reference or customer engineering manuals of the controllers to be used with the system,for programming.

Refer to Section 3 for installation, checkout and operation of the bus expander.

2-1

,(

\

(

"

\

(

INSTALLATION Unpacking

SECTION 3

INSTALLATION AND CHECKOUT

1. Carefully remove wrapping from the AT310-A TTL A/Q-DSA Bus Expander PWA's.

Check for physical damage to each and record damage on the packing list.

Cneck that part. numbers agree with packing list.

2. Remove wrapping from cable and check for physical damage. Record damage on packing list. Check that part number agrees with packing list.

Physical Limitations

Care must be taken to prevent damage to the bus expander PWA's. They must not be f1exed^t bent or dropped.

Power Requirements

The bus expanders require +5 vdc derived from the power supply of the AB107/AB108.

Cabling and Connectors

An external interconnecting flat-cable is available for use between the

controller and the distribution unit. The cable part number is 89821800. It is approximately four feet long.

89758600 A 3-1

Where two sets of expander PWA's are required, two sets of flat cables must be installed.

Cooling Requirements

The expander PWA's are cooled by the forced air system of the enclosure. No further cooling is required. Refer to the computer customer engineering manual (89633300) for further information concerning cooling capabilities of the computer and expansion enclosure.

Environmental Considerations

The environmental considerations necessary for operation (or storage) of the controller cards are listed in Table 1-1.

Preparation and Installation

To install the TTL bus expanders perform the following with the computer power switched "off":

1. Remove the air-flow blocks from lower slide of card slots to be used in both the main and remote enclosures. Refer to Figure 3-1 for selection of the location for PW board.

2. Inspect both enclosures, card slots, PW board slides and connector pins, for physical damage.

3. Place the internal select jumpers in the positions on each PWA's as descrjbed below and shown in Figure 3-2:

3-2 89758600 A

For A/Q expansion:

/,.-/ .. - .. -.-::-:-::=::::.-".~

On the main enclosure PWA (89821600 O(89876~.9J/

1) At Ul, place jumper plugs at 1 and at~both marked M) 2) Below U6-U7 (~rked AQ~), place jumper plug.

3) Below U20, place jumper plug at 6 (marked AQM).

4) At U40, place jumper plugs at 12, 15 and 16 (marked M, M and AQM res pecti ve ly) .

On the remote enclosure PWA (89759200 or ~~.QJ

1) At Ul,place jumper plugs at 2 and at 4 (marked R).

2) Below U6-U7 (marked AQM-DSR) place jumper plug.

3) Below U20, place jumper plug at 5 (marked AQR).

4) Below U34-U35, place jumper plug at 9 (marked R), at 10 (marked AQR) and at 11 (marked R).

5) At U40, place jumper plugs at 13, 14 and 17 (marked AQR, Rand R respectively).

For DSA expansion:

On the remote enclosure PWA (89759200 or 89880700)

1) At Ul, place jumper plugs at 2 and at 4 (both marked R).

2) Below U6-U7 (marked DSR-AQM), place jumper plug.

3) Below U20, place jumper plug at 7 (marked DSR).

4) Below U34-U35, place jumper plug at 9 (marked R) and 11 (marked R).

5) At U40, place jumper plugs at 16, 14 and 17 (marked R, DSR and R respectively).

On the main enclosure PWA (89821600 or 89876000)

1) At Ul, place jumper plugs at 1 and at 3 (both marked M).

2) Below U20. place jumper plug at 8 (marked DSM).

3) Below U34-U35, place jumper plug at 9, 10 and 11 (marked DSM).

4) At U40, place jumper plugs at 12, 13 and 15 (marked M, DSM and M, respectively).

89758600 A 3-3

CAUTION

Do not install cables or expanders PWA's in computer enclosure or expansion enclosure with power on.

4. Interrupt connections are transferred to the computer through the Sint line driver receivers. Connect a wire jumper from the controller Interrupt signal to an available Sint position on Pl of the A/Q expansion position in the remote enclosure. Connect a wire jumper from chosen Sint pin in the computer A/Q expansion enclosure to the required Interrupt position on the CPU.· Refer to Table 3-1 for Interrupt positions available for selection.

5. Scanner connection must be made by connecting wire jumpers from the scanner sections of required controllers through MTR and RTM signals. See Figure 4-3 of Section 4.

Signal MTR is connected to P1B19.

Signal RTM is connected to P1A19.

6. Install expander flat cable(s) on back-plane at P2 in the position assigned.

7. Carefully install the bus expander PWA's ( part no. 89821600 or 89876000 for the main enclosure and 89759200 or 89880700 for the remote enclosure) in each enclosure, making certain that it slides in smoothly.

CHECKOUT

1. Refer to the CPU reference manual, publication number 89633400 and to the reference or maintenance manuals for the controllers used with this expander for progamming and operation of that equipment.

2. Perform diagnostics checks for each of the controllers used with this equip- ment, as described in the Systems Maintenance Moni tor r1anua1 (SMMl7), publi- cation number 60182000.

3-4 89758600 A

ex>

1.0 ...

U'l ex>

0'1 o o

>

W I U'l

36 35

EIGHT MEMORY MODULES

34 33 32 31 30

CENTRAL CARTRIDGE NRZI

PROCESSING DISK MAGNETIC

UNIT DRIVE TAPE

CONTROL- TRANSPORT

LER CONTROLLER

29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12

"

Figure 3-1. Locations of PWA's in Enclosure

PHASE A/Q DSA A/Q

ENCOD-

ING BUS BUS BUS

FOR MAT- TER

10 9 8 7 6 5 4 3 2 I

W I O"l

~ co

'-I Ul co

O"l

o o

>-

£s • • • • • • • • • • • • • • • • • • ' • • • • • • • • • • • • • 1 ~3CJNvdX3 sna 1ll

...-

Figure 3-2. Locations For Jumper Plug Plac~ment

TABLE 3-1. INTERRUPT POSITIONS SIGNAL NAME INPUT/OUTPUT

SINT 1 P1A24

snn

SINT 3 P1A26

SINT 4 P1A27

SINT 5 P1A28

SINT 6 P1A20

SINT7 P1 A31

SINT 8 P1B20

SINT 9 P1B24

SINT 10 P1B25

SINT 11 P1B26

sun

SINT 13 P1B28

SINT 14 P1830

SINT 15 P1831

89758600 A 3-7

SECTION 4 THEORY OF OPERATION

INTRODUCTION

This section presents general and detailed functional descriptions of the equipment, using aids such as overall and detailed block diagrams.

Descriptions are keyed to the detailed logic diagrams in the diagram section (Section 5) and afford"a basis in understanding the detailed description of the specific circuit in that section.

89758600 A

NOTE

It is assumed that the reader is familiar with Control Data equipment and with the programming characteristics of the Computer as described in the 1784 Computer System Reference Manual, Publication Number 89633400.

4-1

GENERAL

The AT3l0-A TTL A/Q-DSA Bus Expander i~ comprized of two standard 50-PAK PWA'3 and a single interconnecting flat cable. Both PWA's use the sampe type of

board, but have different components. The main PWA is installed in the AB107/AB108 enclosure with its jumper plugs placed as described in Section 3, while the

remote PWA (with jumper plugs set) is placed in either the BT148-A expansion enclosure or another suitable enclosure. The function of each expander is set by placing or omitting jumper plugs from the positions shown in Figure 3-2.

Access in and out of the enclosures is made by leading the flat cable through the slots in the case on the backside of the enclosures.

Two sets of bus expanders may be used to extend the capabilities of both the A/Q and DSA buses. The AB107/AB108 will allow the use of a maximum of two expansion enclosures employing both the A/Q and the DSA buses, as shown in Figure 4-1.

ENCLOS URE

1

4-2

(E) A/Q SLOT

---

SLOT

(E)

A/Q SLOT

(E)

I

I

J

AB107/AB108 COMPUTER (MAIN ENCLOSURE)

(E) = EXPANDER PWA

I

I A/Q

ENCLOS- SLOT

URE DSA I ² SLOT

J

(E)

Figure 4-1. Expansion Through Two Enclosures

897f8600 A

CIRCUIT TYPES

The circuits used in the TTL expanders are bi-directional. Signals may enter from PI and exit at P2 or enter P2 and leave at Pl. Four types of line driver circuits are used.

Type 1 utilizes a 146S inverter in series with a 204 inverting AND gate. This circuit is symetrical. Line driver Type 2 uses an inverter (146S) and an inverting AND gate (204) in the circuit from PI to P2, while the signal flow from P2 to PI passes through an inverting Schmitt Trigger (167), shaping the signal first and then through an inverting AND gate. Type 3 uses only inverting AND gates (204¹s) in each of the signal paths and both paths are symetrical.

Type 4 uses a NAND Buffer with the inputs to each AND gate section paralleled in the circuit from PI to P2, and an inverting AND gate (204) in the P2 to PI

circuit.

These circuits are shown in Figure 4-2.

89758600 A _4-3

vee

270

Mounted only on PWA in remote enclosure

'vee

270

- _-

Mounted only on PWA in remote enclosure

4-4

Control Signal Bus to Li ne

__ - - - 1 1465 ~--I---I

a

20~~­

XXX

XXX ~--~

vee

330

... - _ . - - - - ( P2

a

----...&..11..204

I

~--~~146S~~

XXX XXX ^1--__

Control Signal Line to Bus LINE DRIVER - TYPE 1

Control Signal Bus to Line

a

1 ^204~~---

_ -... 1465 I-l---... - - I XXX XXX

a

---~1-204

SCHMITT

1---1

1 7

xxx~--

Control Signal Line to Bus LINE DRIVER - TYPE 2

Figure 4-2. Line Driver Circuit Types

560

VCC 330

89758600 A.

Mounted only in PWA in remote enclosure

vee

Mounted only on PWA in remote enclosure

Control Si gnal Line to Bus LINE DRIVER - TYPE 3

Control Signal Bus to Line

8 204 XXX

8

XXX

JE

Control Signal Line to Bus LINE DRIVER - TYPE 4

vee

330

560

-

Figure 4-2. Line Driver Circuit Types (continued)

P2

89758600 A. 4-5

4-6

PROPAGATION DELAY

The propagation delay, measured between the time the signal at the sending side crosses the 1.5V level and the time the received signal crosses the 1.5V level,

is measured at Pl. For fixed-direction signal flow the propagation delay is less than:

70 nanoseconds for Driver/Receiver TYPE 1 90 nanoseconds for Driver/Receiver TYPE 2

Refer to Fi gure 4-2 60 nanoseconds for Driver/Receiver TYPE 3

50 nanoseconds for Driver/Receiver TYPE 4 FAN-IN AND FAN-OUT

The fan-in on PI in the main frame for all signals, except MTR and RTM in DSA operation, is one TTL Load.

ForMTR, a 560-ohm pull-up resistor is used. For RTM, a combination of a 280-ohm pull-up and a 560-ohm resistor to ground is used.

In the remote enclosure on PI signals, a combination of a 270-ohm pull-up and a 560-ohm resistor to ground is used on each signal except MTR and RTM.

For ,MTR, a combination of a 280-ohm pull-up and a 560-ohm resistor to ground is used.

For RTM, only one pull-up of 560-ohm is used to allow non-buffered components to drive the scanner.

The fan-out on all PI signals in the remote enclosure is 16 TTL Loads.

BASIC PWA DIFFERENCES

The two PWA's used differ basically in the omission of certain components and in the placement of jumper plugs.

The PWA used in the main enclosure mounts a lK resistor at R72 and omits the following components:

U6, Ull, U12, U25, and U30

Rl-R28, R57-R7l, R73-R84, Rl13-R140, R169-R196, R185, and R238.

89758600 A

The PWA used in the remote enclosure mounts a 270-ohm resistor at R72 and omits the following components:

U10, U14, U15, U27, U29, and U33

Jumper plugs are inserted in specific locations on the PWA's to prepare them for use as A/Q or DSA channel expanders in the main enclosure, or as A/Q or DSA channel expanders in the remote enclosure.

To use the PWA's for A/Q or DSA expansion, refer to Section 3 for placement of the jumper plugs.

89758600 A 4-7

I

INTERRUPT AND SCANNER CONNECTIONS Interrupt Connection

The Interrupt signals from the remote controllers are transferred via the Sint signal line driver receiver. See Section 3 for selection of Interrupts.

DSA Scanner Connection

The scanner connection is made by placing jumpers between the input/output scanner signals of the DSA scanner and the appropriage connections at Pl of the expander PWA. These connections are made on the back-plane of the enclosure.

Two signal lines are used for the scanner, MTR, allowing signal flow from the main frame to the remote, and RTM operating in the reverse direction.

A typical connection is shown schematically in Figure 4-3.

89758600 A

I

I

PII P2

0 - SFI SFO

.. -

.. -

FIRST MIDDLE I

0 - SRI SRO

-

_I"

- --

CONTROLLERS : EXPANDER

EXPANSION ENCLOSURE 1

.. _-

- -

I

:

I ^I

- ^-

^{- -}

^r+

^{.. -}

I MIDDLE MIDDLE I

..

..

..

P2- MTR

Tpi SRI SRO SRI SRO ":t- RTM _{- ~I-}

PII P2

EXPANDER: CONTROLLERS : EXA\NDER

MAIN (CPU) ENCLOSURE

.. - -

I I

1"'1-

.. -

.. -

I MIDDLE LAST

-

-

P2

--

-

EXPANDER : CONTROLLERS

SFO - SCAN FORWARD OUT SFI - SCAN FORWARD IN SRO -SCAN REVERSE OUT

SRI -SCAN REVERSE IN

89758600 A

EXPANSION ENCLOSURE 2

MTR-SCAN MAIN TO REMOTE RTM-SCAN REMOTE TO MAIN

Figure 4-3. Scanner Connections

4-9

SIGNAL ROUTING

The direction of signal flow of all signals except data lines is determined by jumper plugs set on the expander PWA's according to PWA use (A/Q main, A/Q remote, DSA main, DSA remote). The data signal flow direction is determined by the combination of the jumper plug settings and the state of the Read signal for A/Q expansion, or the Write Enable for DSA expansion.

Refer to Section 3 and Figure 3-1 for location of the positions for the jumper plugs.

The following lists provide the signal data flow direction:

A/Q expansion

Data lines: Normally flowing from main enclosure to remote enclosure. When the Read signal is present the direction is reversed.

Signals from main enclosure to remote enclosure:

Address lines, Timing Pulse,

Me,

Signals from remote enclosure to main enclosure:

Sint lines, Char Input, Reject, Reply DSA expansion

Data lines: Write Enable active from remote enclosure to main enclosure

Write Enable not active from main enclosure to remote enclosure

Signals from main enclosure to remote enclosure:

Protect Fault, Autoload, MC, Resume, Par Error, Par Bit, Protect Bit, 65K Memory, SMTR.

Signals from remote enclosure to main enclosure:

4-10

MemorY.Address lines, Request, ~P-rl~·0-r-'i7ty-, Protect, Write Enable, SRTM.

89758600 A

KEY TO LOGIC SYMBOLS

(

SECTION 5 LOGIC DIAGRAMS

Publication 89723700 (Key to Logic Symbols) or equivalent, lists the symbols used in the logic diagrams in this manual and gives a short description of the functions they represent. The symbols conform generally to Control Data usage

(Microcircuit HandboQk, publication number 15006100), using the polarity logic convention.

The following paragraphs describe the signal flow conventions used.

SIGNAL FLOW

Input signals are drawn coming from the left or above; output signals are drawn going to the right or down.

The signal lines are sometimes interrupted to allow logical grouping of components.

is used:

89758600 A

At ~ach such interruption one of the following indicators

On-Sheet Continuation Reference Symbols

These symbols when used with the logic symbols in the following diagrams indicate that a connection exists between two points on a sheet. The arrows attached to each circle point from signal origin to signal des tina t ion. The letters, C, H, I, 0 and P are not used inside the circles, since they bear special significance on

logic diagrams.

5-1

(ON SHEET 2)

---@3.6

2.3

0 - -

(ON SHEET 6)

OR

5-2

Off-Sheet Continuation Reference Symbols

These symbols when used with the logic symbols in the following diagrams indicate that a common signal point exists between two sheets in a series of related drawings.

These symbols point from output to direction of input as show~ in the illustration. The

letters C, H, I, 0 and P are not used in the hexagons, since they bear special significance on logic diagrams. The number(s) next to each hexagon indicate the sheet(s) that the signal is continued from or on. For instance, the numbers 3.6 refer to sheets 3 and 6, while 2.3 refers to sheets 2 and 3. It should be noted that the referenced sheet number(s) is always placed opposite the line extending from the hexagon. The sheet number where the signal originates is underlined.

Test Points

The test point symbol on the logic diagram shows the connection of a test point on the printed wiring board (PWB). The number adjacent to the symbol refers to the test point position on the PWB at the edge opposite the connectors. Only test point one is labeled on the edge of the PWB.

89758600.A

NON - CONNECTING LINES

Connectors

CONNECTING LINES

Connecting and Non-Connecting Lines

Lines connected to a common point or at a junction point are shown in the upper part of this illustration. No more than four

lines are connected to a common point in the diagrams.

Lines crossing but not connected are shown in the lower part of this illustration.

Connectors are represented on the logic diagram by the symbol for a female connector, for both input and output signals. The name of the signal is placed in the open end of the connector symbol (shown below), using the full name of the signal or the common abbreviation appl icable to logic diagrams.

The connector number, pin row and pin number are located above the 1 ine extending from the connector symbol.

READ

>>-P_I_!_~_:---

89758600 A

SIGNAL NAME

CONNECTOR NUMBER PIN ROW

PIN NUMBER

5-3

LOGIC DIAGRAM 89759000

Each circuit of the AT3l0-A TTL A/Q-DSA Bus Expander is bi-directional. The flat cable is connected from P2 of one enclosure to P2 of the other. The presence or lack of jumper plugs determine the direction and conditions of signal flow.

As stated in Sections 3 and 4, during use in the main enclosure PWA 89821600 will have all jumper plugs marked M installed. PWA 89759200, mounted in the remote expansion enclosure will have all jumper plugs marked R set.

When the PWA in the main enclosure is used for A/Q expansion, all jumper plugs marked AQM will be set and the PWA in the remote enclosure will have all AQR

jumper plugs set.

For DSA operation the main enclosure PWA will have the DSM jumper plugs set and that installed in the remote enclosure will have the DSR jumpers set.

The jumper plugs are used to either enable or inhibit the inverting AND gates in one-half of circuitry or the other, causing the signal flow to occur from Pl to P2, or from P2 to Pl. The gate(s) shown in the logic diagrams, herein, in the upper part of each circuit allows the signals to flow from Pl to P2, when enabled. At this time the AND gate(s) shown in the lower part of each circuit will be inhibite~. For signal flow from P2 to Pl, the lower half of each circuit is enabled and the upper half inhibited. Control of all but the data circuitry, inhibiting or enabling one half or the other, is accomplished through the jumper plugs set at U40. Flow of data in either direction is controlled by the READ/WRITE circuitry (sheet 5 and sheet 2, lower half)

The circuitry used herein is of the four types described previously in Section 4.

89758600 A 5-4

00 u:.

-....J U1 00 0'\

0 0

»

I

REFERENCE LETTERS - RI

R2 MI M2 Y NY Z NZ A 8 C 0

.

I

,\

U1 I U1

SHEET L'CATIONS 2

"

0-1 ... C-4 C-4 0-3

0-1'" 8-4 8-4 8-4 c-;!

0-1. 0-4 8-4 8-3

C-19 8-4 0-4 C-4

C-I", 0-4 C-4 ...!.:!.

C-I. C-4 8-4 10-4

A-I. 0-4

A-I", C-4

B-2 8-"'"

8-2 C -3.

8-2 B-391

B-2 10-3 ...

P2A" I

+5V)

J I

.. C9 C2 .. C8

~ ~;:F 'T' 68 NF GND} P2A_29___ .

aND) PI8U 8HD) P2A05

8HD) P2821

i

i ~

10 0 0

.. ..

I:

NGITES'

1 SHEET REVISION STATUS

laoToJjj6111:1~;;41

REVISION RECORD

.

DESCRIPTION IDAFT r"TE IClOCDI ...

REDRAWN TO CDC STD R 72 IN MAIN PWA ADDED I,," 1"-"" 1_1)1; \rI~' ..

1m ^[rJ I

A A A A A A IIIIIH5NY.HIDSHS"

1M 2 : IN '.ADDED TO Itl AND II IN I ADDED TO NY

:~~'. ~i~~:,~ U:'~:;J:~'

1t10_. R211, PZI07 IMS "-4 INPUT NY ADDEO AT UIS-IO OUTPUT 0 ADDED AT U22-12

f04lCK 1072 :::~~: :'E:::'~ 'OR RE'iO!

[<ToKIO.'

TO FIT "SSY. THREE SEPARATE

CIRCUITS ot4 NEW SH6 REPLACE

I I 1A

GENERAL CIRCUIT AND TABLE ON l. J'.". /J

~'rxEL~~~\RIGHT(CONYERSK'IN... _ q ...

ISHEET LOCATIONS FOR RI,R2.MI

~N.!._U~~.~TED IN SHI TABLE, _ ERRORS CORRECTED NO lOGIC CHANGES.

[)£TAILS IN [CO ,,~I~\'iG1iA

I

I. SIGNAL REFERENCES IN TABLES AND qlNNECTORS:

z'

0,

NA INDICATES NIl SIGNAL TRANSMITTED, UPPER SIGNAL NAMES IN TA8LES AND liN CIINNECTORS

REFER TI! A/Q SIGNALS WHEN PWA IS USED TG EXPAND A/Q

L'WER SIGNAL NAMES IN. TABLES AND liN CGNNECTGRS REFER U DSA SIGNALS WHEN PWA IS USED Til EXPAND OSlo,

NGIT MGUNTED IN REM!IlTE PWA, UIO, UI4, U15, U27,U29,U33 NIIT MII)UNTED IN MAIN PWA, us, un, U12, U25, U30

4, ... DENOTES SIGNAL ORIGIN 5, ALL RESISTORS ARE Y4 ^{WATT, 5%}

- - - -

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