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Validation of Mixed Signal-Alpha Real-Time Systems through Affine Calculus on Clock Synchronisation
Constraints
Irina Smarandache, Thierry Gautier, Paul Le Guernic
To cite this version:
Irina Smarandache, Thierry Gautier, Paul Le Guernic. Validation of Mixed Signal-Alpha Real-Time Systems through Affine Calculus on Clock Synchronisation Constraints. World Congress on Formal Methods in the Development of Computing Systems (FM’99), Sep 1999, Toulouse, France. pp.1364- 1383, �10.1007/3-540-48118-4_22�. �hal-00548887�
Validation of Mixed
Signal-
AlphaReal-Time Systems through Ane Calculus on Clock
Synchronisation Constraints
Irina M. Smarandache
1, Thierry Gautier
2, and Paul Le Guernic
21
The University of Reading, Department of Computer Science Whiteknights, PO Box 225, Reading RG6 6AY, United Kingdom
Tel.: (44) 118 931 8611 (7626), Fax: (44) 118 975 1994
I.M.Smarandache@reading.ac.uk
2
IRISA-INRIA, Campus de Beaulieu, 35042 Rennes Cedex, France
Thierry.Gautier@irisa.fr, Paul.LeGuernic@irisa.fr
Abstract.
In this paper we present the ane clock calculus as an exten- sion of the formal verication techniques provided by the
Signallan- guage. A
Signalprogram describes a system of clock synchronisation constraints the consistency of which is veried by compilation (clock cal- culus). Well-adapted in control-based system design, the clock calculus has to be extended in order to enable the validation of
Signal-
Alphaap- plications which usually contain important numerical calculations. The new ane clock calculus is based on the properties of ane relations in- duced between clocks by the renement of
Signal-
Alphaspecications in a codesign context. Ane relations enable the derivation of a new set of synchronisability rules which represent conditions against which syn- chronisation constraints on clocks can be assessed. Properties of ane relations and synchronisability rules are derived in the semantical model of traces of
Signal. A prototype implementing a subset of the synchro- nisability rules has been integrated in the
Signalcompiler and used for the validation of a video image coding application specied using
Signaland
Alpha.
1 Introduction
Real-time systems, and more generally reactive systems [4], are in continuous interaction with their environment. Therefore, they must respond in time to external stimuli. Moreover, real-time systems must be safe, thus one would wish to prove their correctness. Time constraints and safety are two important aspects to be considered in the design of a real-time application.
Real-time systems may be constrained by very tight real-time deadlines.
Moreover, a hardware implementation of parts of these systems is sometimes
required, to meet specic constraints for instance. An example is an application
consisting of numerical calculations performed iteratively on large structures of
regular multidimensional data. In this case, a hardware/software implementation
may be envisaged, in which the numerical calculations are conveyed to hardware
for eciency reasons, while the control relating these parts is implemented in software.
In general, designing a mixed hardware/software real-time system requires a rigorous methodology that comprises methods and tools addressing, among oth- ers, system specication and validation, optimal code generation and hardware synthesis. These aspects are dealt with in codesign [7] [9] which denotes the spec- ication, validation and implementation of an application which consists both of a hardware part, in the form of a set of specialised integrated circuits, and a software part implemented on general programmable processors. The idea is to explore various possible implementations of hardware/software systems in order to improve their performance and to ensure the respect of cost constraints.
1.1 Real-Time System Codesign
System codesign is a complex process which can be decomposed into three main activities [7]: 1. The cospecication of an application at various levels of abstrac- tion; 2. The validation of a specication by formal verication or simulation, also known as cosimulation; 3. The hardware/software partitioning of an application, the evaluation of a partitioning from the point of view of the time constraints and cost, the generation of executable code, the synthesis of hardware, and the production of the interface between hardware and software, i.e cosynthesis. A lot of work has been done, the purpose of which was to dene a well-structured methodology for codesign [7] [11] [19]. An important point was generally the description of both hardware and software using the same language, like for in- stance
Vhdlenhanced with mechanisms for calling
Cfunctions [14], or high-level languages like
C,
C++or
Fortranextended with facilities for the description of hardware systems [10]. These approaches enable the programming of both the hardware and software parts of a system in a unique framework and their vali- dation by simulation. However, they cannot guarantee system correctness. This aspect can be much improved by using formal languages for system specication, renement of specications towards lower levels of abstraction (implementation) and validation of the various specications by formal verication.
Dening a complete methodology of codesign requires addressing other rel- evant problems, most of them concerning cosynthesis. Among these problems there are the automatic partitioning into hardware and software, the synthesis of hardware and the generation of optimal code for software implementation.
The work presented in this paper is part of a more general eort for building a hybrid framework in which the
Signal[12] [13] and
Alpha[20] languages can be used for real-time system codesign.
1.2 Cospecication and Cosimulation of
Signal-
AlphaSystems
Signal
is a synchronous [4] language developed for the specication, validation
and implementation of real-time systems.
Signalvariables represent nite or
innite sequences of values (data) which can be ltered or merged before being
submitted to classical boolean or mathematical operations. A clock is implicitly
associated with each
Signalvariable: it represents a set of temporal indices which denote the logical instants where the variable is present and has a value.
The semantics of a
Signalprogram can be described by a system of constraints (relations) on clocks and values, which is constructed and veried for consistency during compilation. The verication of the clock constraints is called clock cal- culus. The
Signalenvironment is enhanced with tools for
C[5] and
Vhdl[3]
code generation and formal verication of dynamic properties [2].
In its present form,
Signalis well-adapted for the design of control-based real-time systems. Firstly, this is due to its limitations concerning the treatment of computations on multidimensional data such as matrices. Only simple algo- rithms can be expressed in
Signaland no signicant optimisation is performed at the level of the generation of executable
Cor
Vhdlcode concerning vectors.
In contrast with
Signal, the
Alphalanguage has been developed primarily for the specication and implementation of algorithms on multidimensional data.
Such algorithms can be described in
Alphausing ane recurrence equations over convex polyhedral domains [20] and be further transformed for optimal hardware or software implementation on parallel or sequential architectures [21].
Given their complementary properties, the
Signaland
Alphalanguages can be used jointly for the design of real-time systems containing important numerical calculations on multidimensional data and control: numerical compu- tations are expressed in
Alphaand the control is conveyed to
Signal. When the real-time requirements of the system are very tight, a mixed hardware/software implementation may be envisaged. In [9] we propose a hybrid framework for the combined use of
Signaland
Alphain real-time system codesign. In order for this framework to be operational, it is necessary to interface
Signaland
Alphaprograms both at the functional and architectural level. The former corresponds to a high-level mathematical representation of an algorithm in
Alpha, while the latter contains a set of new temporal indices corresponding to the execution of the algorithm on a parallel or sequential architecture.
In
Signal-
Alphasystems, the renement of an
Alphaprogram from a functional level to an architectural level oriented toward a particular implemen- tation also induces a renement of the temporal indices in
Signal. The new time indices are obtained through ane transformations on the instants of time of the initial
Signalspecication. Consider clocks
cand
c1in
Signalwhich are identical at the functional level (they are also denoted as synchronous). Af- ter renement, their relative position is such that clock
c1can be obtained by an ane transformation applied to clock
c: the instants of time of
cand
c1, denoted respectively
Tand
T1, can be described by a pair of ane functions
T
=
fnt+
'1j t2Tg,
T1=
fdt+
'2 jt2Tg, on the same set of instants
T. With
'=
'2 '1, we will say that clock
c1is obtained by an (
n;';d)-ane transformation applied to clock
c, where
n;d 2IIN
the set of strictly positive integers and
'26Z the set of integers. Clocks
cand
c1are also said to be in an (
n;';d)-ane relation.
Clocks obtained by ane transformation may be re-synchronised at the ar-
chitectural level. As an example, consider clocks
c,
c1and
c2which are identical
in the
Signalfunctional specication. At the architectural level, clocks
c1and
c
2
have been transformed such that
c,
c1and
c,
c2are respectively in ane relations of parameters (
n1;'1;d1) and (
n2;'2;d2). Whether clocks
c1and
c2can be re-synchronised depends on the properties of the ane relations which are induced from the values of (
n1;'1;d1) and (
n2;'2;d2). Moreover, the rela- tions between
c,
c1and respectively,
c,
c2may be expressions on (
n;';d)-ane relations constructed using operations like composition, union, etc. In this case, the re-synchronisation of clocks
c1and
c2depends on the properties of these operations.
The
Signalclock calculus performs the verication of clock synchronisation constraints using a set of synchronisability rules, i.e. conditions against which these constraints can be assessed. The current clock calculus depends on boolean equation resolution methods [5] [1] which have been successfully used for the val- idation of numerous control-based real-time applications. However, in order to validate mixed
Signal-
Alphasystems as presented above, it is necessary to ex- tend the current clock calculus with a set of synchronisability rules deduced from the properties of (
n;';d)-ane relations. The new set of rules denes the ane clock calculus, which constitutes the main topic of this paper. We explore the space of (
n;';d)-ane relations and study to which extent it is closed under the main operations that can be performed on ane relations. Following this study, we dene a set of synchronisability rules which, although incomplete, enables the validation of the principles underlying the cospecication and cosimulation using
Signaland
Alpha. The semantical model of traces of
Signal[12] [16]
constitutes the support for the study of the properties of ane relations and for the denition of the new synchronisability rules.
1.3 Organisation of the Paper
In Section 2 we present the integration of
Signaland
Alphafor system code- sign. Section 3 is the central core of this paper and is dedicated to the denition and implementation of the ane clock calculus. The main concepts useful for this purpose are progressively introduced: these are the model of traces of the
Signal
language, the properties of ane relations on clocks, the set of synchro- nisability rules induced by the latter, and nally the necessary elements for the integration of the ane clock calculus in the compiler. The ane clock calculus has been applied to the cospecication and cosimulation of a video image coding application; this is briey illustrated in Section 4. In the same section we discuss in which way the
Signaland
Alphaenvironments may further contribute to the development of a complete codesign methodology based on both languages.
Finally, in Section 5 we present conclusions and perspectives of our work.
2
Signaland
Alphain Real-Time System Codesign
Figure 1 summarizes the main elements of the environments around
Signaland
Alpha
that make both languages well-adapted for real-time system codesign.
Signal
and
Alphaprograms represent mathematical notations for the proper- ties of the processes they dene. The system of constraints on clocks and values associated with a
Signalprogram is transformed by compilation into a synchro- nised data ow graph (
Sdfg). This data structure constitutes the support for executable code generation (
Cor
Vhdl) or verication of dynamic properties using the formal tool
Sigali[2].
The
Alphacompiler includes a powerful type checking mechanism based on the structure of an
Alphavariable as a function over convex polyhedra. The syntax tree obtained after compilation can be directly translated into
Ccode for functional simulation, or it can be transformed into a subset of
Alphacalled
Al-pha0
which exhibits the details of a parallel or sequential implementation. The syntax tree in
Alpha0form can be further translated in
Cor
Vhdlexecutable code or directly mapped on a netlist [21].
The interface between
Signaland
Alphais based on the fact that both languages can be translated in
Cand executed for functional simulation. Fur- thermore,
Signaloers the possibility to call external processes: such a process can be the specication of an algorithm in a language other than
Signal. A particular type of an external process is a function, the execution of which is considered instantaneous from the point of view of
Signal. A
Signalfunction can be a predened or a user-dened
Cfunction.
Fig.1.Signal
and
Alphain system codesign.
2.1 Functional Cospecication and Cosimulation
Being a synchronous language,
Signalis based on the following hypotheses [4]:
1. All actions (communications and calculations) in a system have zero logical
duration (the elapsed time is represented by the precedence of successive values on a same data ow); 2. Two or more actions can take place at the same logical instant, such actions being termed \simultaneous". From the point of view of the logical temporal properties of a system, only succession and simultaneity of instants are of interest. Although their exact time values are not considered, note however that they will be considered for a given implementation. The pro- cess associated with a
Signalprogram represents thus a succession of logical instants, with each instant being associated one or more actions considered of zero logical duration and involving process variables present at that instant.
Consider for example a coding system for sequences of video images at 34 Mbits/s [8]. A system of this type consists of a set of numerical treatments applied iteratively on images of the same dimension. Images are divided into luminance and chrominance blocks and treatments are applied to each block.
Numerical treatments consist mainly of algorithms for inter and intra image coding which require operations like a discrete cosine transformation (
Dct). In order to illustrate the interfacing between
Signaland
Alpha, we have isolated from the coding application a simple
Signalprogram and have illustrated the associated process in Fig. 2. It consists of a
Dctoperation applied in sequence to dierent values
Aiof the matrix of pixels
Apresent at each logical instant of time
t
i
. The matrix
Acorresponds to a block of luminance or chrominance of an image.
The
Dctcan be expressed in
Signalas
B:=
Dct(
A), where
Dctis actually an external process. The
Dctis a time consuming algorithm, particularly for large matrices or when applied to images containing a large number of blocks. In order to improve the overall performance of the coding application, one would wish to execute each instance
Bi:=
Dct(
Ai) on a parallel integrated architecture as derived by the
Alphaenvironment.
The
Dctcan be easily described in
Alpha. The
Signal-
Alphacospecica- tion and cosimulation of the new system is made possible at the functional level as follows (see Fig. 2): 1. The
Alphasystem is translated in executable
Ccode;
2. The
Cfunction ALPHA C obtained at step 1 represents the external process implementing the
Dctin
Signal. The function ALPHA C is considered instan- taneous in
Signal; the clocks of the matrices
Aand
B, denoted respectively by
c
and
c1, are therefore synchronous. The overall system is thus represented as a
Signalspecication executing instantaneously the functional description of the
Alphaspecication. The system can be validated in the
Signalenviron- ment by formal verication (compilation, model checking with
Sigali) and/or simulation.
2.2 Implementation-oriented Cospecication and Cosimulation
A mixed
Signal-
Alphaspecication at the functional level may be rened in order to take into consideration the details of a particular implementation. The
Alpha
program of Section 2.1 describing a
Dctmay be submitted to a sequence
of transformations for a parallel or sequential implementation. These transfor-
mations guarantee the equivalence of the nal specication, noted ALPHA' in
Fig. 3, with the initial ALPHA system of Fig. 2. The system ALPHA' contains
Fig.2.Signal
-
Alphainterface at functional level.
the time indices corresponding to a particular scheduling of the
Dctoperation.
In Fig. 3 these time indices are represented as the diagonal sets of micro-instants
t j
i
associated with each macro-instant
ti.
The
Signalspecication has to be rened accordingly in order to enable the validation of the overall system. Therefore, the micro-instants of time of ALPHA' are taken into consideration in the new process SIGNAL' and described as the sets of instants
Sti0,
Sti1, etc. (see Fig. 3). The
Cfunction ALPHA' C has been derived from ALPHA' and transformed in order to describe the sequence of operations performed at each micro-instant of time.
Fig.3.Signal
-
Alphainterface at architectural level.
The regularity of
Alphavalues manifests itself in
Signalin several ways.
First, the sets of micro-instants
Sti0,
Sti1, etc. have the same cardinality. Also, successive values for
Bare provided at specic micro-instants between any two successive macro-instants
tiand
ti+1in a regular manner. This situation is il- lustrated in Fig. 4 where the clocks of matrices
Aand
B, denoted respectively by
cand
c1, are dened by the following instants of time:
c=
f0
;9
;18
;:::gand
c
1
=
f6
;15
;:::g(after providing the values
Biat the instants of time dened by
c
1
, the architecture implementing the operation
Bi:=
Dct(
Ai) may execute fur-
ther computations like initialisations for the next operation
Bi+1:=
Dct(
Ai+1)).
Fig.4.
Illustration of an ane relation.
In Fig. 4, clock
c0is dened by the set of instants
f0
;1
;2
;3
;4
;5
;:::g. It can be noticed that clocks
cand
c1are placed in a regular manner on the sup- port clock
c0: their relative position is such that
c1has been obtained through an (9
;6
;9)-ane transformation applied to
c. By denition, clock
c1is the re- sult of an (
n;';d)-ane transformation applied to clock
cif it can be obtained from
cthrough steps 1 and 2 as follows: 1. Constructing a new clock
c0as the union of
cwith the set of instants obtained by introducing
n1 ctive in- stants between any two successive instants of
c(and
'ctive instants before the rst instant of
cwhen
'is negative). 2. Dening the clock
c1as the set of instants
fdt+
'jt2c0g, with
c0=
ftjt2IIN
g(in other words, counting ev- ery
dinstant, starting with the
'thinstant of
c0, or with the rst instant of
c
0
when
'is negative). Clocks
cand
c1are then said to be in an (
n;';d)- ane relation. The above denition can be expressed in an equivalent form as follows: clocks
cand
c1are in (
n;';d)-ane relation if there exists a clock
c
0
such that
cand
c1can be respectively expressed using the ane functions
t:
(
nt+
'1) and
t:(
dt+
'2), with
'2 '1=
', with respect to the time in- dices of
c0:
c0=
ftjt2IIN
g,
c=
fnt+
'1 jt2c0g,
c1=
fdt+
'2 jt2c0g.
Properties on ane relations can be exploited in order to verify that clocks are synchronisable, that is, their sets of instants can be identied (re- synchronised). Consider (Fig. 2) a
Signalprogram which executes two succes- sive
Dctoperations at each macro-instant
ti, one on a luminance block of an image, noted
B:=
Dct(
A), and the second one on the next block of red chromi- nance of the same image, described by
D:=
Dct(
C).
Each
Dctfunction is expressed in
Alphaat the functional level and further rened according to a particular implementation. The
Signalspecication is rened accordingly and we obtain the timing diagrams of Fig. 5: the clocks of
Aand
Care synchronous and equal to
c, the clocks of
Band
Dare respectively
c
1
and
c2, and the clocks
c0and
c00describe the instants of the excution of the
Dct
functions on a potential architecture derived in the
Alphaenvironment.
In the functional
Signal-
Alphaspecication, clocks
c,
c1and
c2were syn-
chronous (see Section 2.1 for details). After renement of the time indices in
the
Signal-
Alphaspecication, the clocks
c1and
c2should be re-synchronised
in order to preserve the temporal properties of the whole application. Whether
the re-synchronisation of
c1and
c2is possible given their relative position as
illustrated in Fig. 5, or after further adjustments of their time indices, can be
decided based on the properties of the ane relations existing between
c,
c1Fig.5.
Synchronisable clocks in the context of codesign with
Signaland
Alpha. and
c,
c2respectively. Clocks
c,
c1and
c,
c2are respectively in (9
;6
;9) and (7
;3
;7)-ane relation in the process SIGNAL'. The relation existing between the triplets (9
;6
;9) and (7
;3
;7) guarantees the equivalence of the corresponding ane relations. This will be detailed in Section 3. Informally, the equivalence of the above ane relations expresses the fact that the relative positions of clocks
c
and
c1, respectively
cand
c2, are identical. Based on this observation, clocks
c
1
and
c2can be identied without contradicting the temporal behaviour of the other clocks in the
Signalprogram. The instants of time of clocks
c0and
c00situated between two successive instants of
cand
c1(or
c2) are independent and can be positioned with respect to each other in various manners; in Fig. 5 we have illustrated one possibility. Therefore,
c1and
c2can be re-synchronised; we say that
c1and
c2are synchronisable.
The aim of the ane clock calculus discussed in Section 3 is to dene neces- sary and sucient conditions for clock synchronisability based on the properties of ane relations on clocks. These conditions are expressed as a set of synchro- nisability rules and are derived in the semantical model of traces of
Signal. Section 3 begins with an introdution to these concepts.
3 Ane Calculus on Clocks in
SignalFigure 6 introduces the reader to the semantics of traces [12] [16] of
Signal. The most important concepts in
Signalare: 1. the signal, which denotes a variable of the language and represents a nite or innite sequence of values;
2. the clock, a variable associated with each signal which represents the set of
logical instants where the values of the signal are present.
Signaloperators
manipulate signals by imposing implicit or explicit constraints on their values
and clocks. Constraints on clocks are usually expressed as identities between
clock expressions constructed using the operators of intersection (
^), union (
_) or dierence (
n). Clocks can be also subsets of other clocks dened as samplings by boolean conditions. When no condition is explicitly or implicitly stated on a pair of clocks, they are independent.
Fig.6.
Illustration of
Signalsemantics of traces.
A
Signalprogram describes a real-time system, which is in continuous inter- action with its environment. Input values are transformed corresponding to the actions of a given specication and the results are provided to the environment.
This situation is illustrated in Fig. 6 in the case of a program manipulating in- puts
xand
yand providing output
zdepending on the values of
xand
y. In case
z
is the addition of
xand
y, signals
x,
yand
zare implicitly constrained by the + operator in
Signalto have the same clocks
cx=
cy=
cz.
The congurations
Fand
F0illustrated in Fig. 6 correspond to two dierent executions of the
Signalprogram, involving sequences
xi,
yiand
ziand respec- tively
x0i,
yi0and
zi0. The set of all possible congurations, called traces, which can be exhibited during the execution of a
Signalprogram, denes completely the process
Passociated with the program. Consider
Aa subset of the set
Bof signals manipulated by a program. A trace may contain instants with no action involving signals from
A. However, each instant of this type contains actions which involve other signals from the set
BnA. Given a subset
Aof signals, a ow on
Ais a trace with at least one action involving signals from
Afor each logical instant. In the particular case of Fig. 6, if we consider the subset of signals to be
fx;y;zg, the traces illustrated are actually ows.
More generally, the process
Passociated with a
Signalprogram is a set of
ows on the variables of the program. Each ow
Fin
Pis constrained by a system
of equations on the clocks and values of signals manipulated by
P. Equations
on values can be further expressed in the abstract form of a data dependency
graph (an example of a data dependency graph is illustrated in Fig. 6 for the +
operator). Besides the clock calculus, the compiler veries data consistency by checking the absence of cycles in the data dependency graph. In the next section however, we will concentrate mainly on the clock calculus.
3.1 Clock calculus & Synchronisability
The clock calculus is equivalent to the resolution of a system of clock equations.
For example:
c
=
c1c
0
= (
c1^c2)
_c1c
=
c0(1)
can be a system derived from a
Signalprogram which manipulates clocks
c,
c0,
c
1
and
c2. In this simple system,
c1and (
c1^c2)
_c1have clearly to be proved equivalent, which is an immediate consequence of the axioms of the boolean lattice. The space of clocks associated with a
Signalprogram is a boolean lattice [6] the properties of which are extensively used for the proof of equivalences. The resolution of the system is performed by triangularisation of the system [5] [1].
Given a boolean signal
Cd, its clock, denoted ^
Cd, can be partitioned into the clock [
Cd] where the signal
Cdis present and true and the clock [
:Cd] where
Cdis present and false (the clocks [
Cd] and [
:Cd] represent samplings by boolean conditions). The relations between clocks ^
Cd, [
Cd] and [
:Cd] are expressed by the partition equations below:
[
Cd]
_[
:Cd] = ^
Cd[
Cd]
^[
:Cd] =
;(2)
The axioms of the boolean lattice together with the partition equations induce on the space of clocks a lattice of an order
\coarser" than the order
of the boolean lattice [5]. Clocks can be boolean formulas constructed either with samplings by boolean conditions [
Cd], [
:Cd] or with free variables of the boolean lattice. The properties of the lattice of order
are actually used during the triangularisation of any system of clock equations.
The axioms of the lattice
represent a system of synchronisability rules in the sense described below. Clocks
cand
c0are synchronisable in the process
P, which is denoted by
c P c0, if there exists a ow
Fin
Pin which
cand
c0are synchronous:
c P
c 0
,9F 2P;c
=
F c0(3)
(we note
c=
F c0the fact that
cand
c0are synchronous in
F).
Whenever the property expressed by equation 3 is valid for each ow
Fin
P, the clocks
cand
c0are said to be synchronous in
P, which is denoted by
c=
P c0. This denition can be expressed as follows:
c
=
P c0,8F 2P;c=
F c0(4)
Unless explicitly constrained through the
Signalprogram, clocks
cand
c0are completely independent in the associated
Pprocess. Therefore, their relative position can be such that in some ows
Fin
Pthey are identical, while in some other ows
F0in
Ptheir instants interleave in an arbitrary manner: obviously, if
cand
c0are independent in
P, they are synchronisable. When the relative position of clocks
cand
c0is implicitly or explicitly constrained by the
Signaloperators, ows
Fin
Pare subsequently constrained and the synchronisability of
cand
c0depends on these constraints.
In order to better understand the use of the synchronisability rules, consider for example a process
Pderived from a
Signalprogram Prg in which clocks
cand
c0are dened by the rst two equations of the system (1):
c
=
c1c
0
= (
c1^c2)
_c1(5)
Program Prg may be transformed into Prg
0in which an additional constraint has been expressed on clocks
cand
c0:
c=
c0(in the
Signal-
Alphacontext, Prg could be part of a transformed
Signal-
Alphaspecication, as seen above, and Prg
0the same specication, in which clocks are resynchronised). Consider the process
P0corresponding to the program Prg
0. The system of clock equations associated with Prg
0is (1). Given the set of ows
F0Psuch that
c=
F c0,
8F 2F
0
, it results
P0=
F0. Therefore, verifying the consistency of (1), which is equivalent to testing that clocks
cand
c0are equivalent in
P0, is further equivalent to testing the synchronisability of
cand
c0in
P. The rule (
c1^c2)
_c1=
c1from the boolean lattice is indeed a synchronism rule: (
c1^c2)
_c1=
P c1for every process
P. The same axiom holds for the process
Passociated with Prg. And thus (
c1^c2)
_c1 P c1, since synchronism implies synchronisability. Therefore in the example,
F0is not empty and it can be concluded that
P0is consistent from the point of view of the constraints expressed on its clocks.
The rules of the lattice
represent synchronisability rules: each identity
f
1
=
f2, with
f1,
f2boolean formulas on clocks, is equivalent to
f1=
P f2which implies
f1P f2for every process
P. These rules can be further extended using the properties of the ane relations between clocks. Figure 5 illustrates this idea:
if
Pis the process associated with the program SIGNAL', the conguration in which clocks
c1and
c2coincide represent a ow
F 2Psuch that
c1=
F c2. Thus,
c1and
c2are synchronisable in
P. The reason here is that the (9
;6
;9) and (7
;3
;7)- ane relations existing respectively between
c,
c1and
c,
c2are equivalent. In the next section, we dene the ane relation associated with a ow and a process and further explicitate the concept of equivalence of ane relations.
3.2 Ane Relations in
SignalGiven
n;d2IIN
and
'26Z xed, clocks
cand
c1are in (
n;';d)-ane relation in
the ow
F|which is denoted
cRF(n;';d)c1or (
c;c1)
2RF(n;';d)|if the relative
position of
cand
c1in
Fcan be induced by an (
n;';d)-ane transformation as dened in Section 2.2.
Clocks
cand
c1are in (
n;';d)-ane relation in process
P, denoted
c R P
(n;';d) c
1
or (
c;c1)
2 RP(n;';d), if they are in (
n;';d)-ane relation in each ow
Fof
P, i.e.
cRF(n;';d)c1,
8F 2P. Flows and processes are dened over the set of variables they manipulate. For a given set
A, a ow
Fon
Ais a member of the set of ows
FAthat can be constructed with the variables of
A. In a similar manner, a process
Pon
Abelongs to the set of processes on
A, i.e.
P 2 PA. Because of the nite nature of the sets of variables associated with ows and processes, ane relations can be dened as nite sets as follows:
8F 2F
A
;R F
(n;';d)
=
f(
c;c1)
2AAj cRF(n;';d)c1g(6)
8P 2F
A
;R P
(n;';d)
=
f(
c;c1)
2AAj cRP(n;';d)c1g(7) Consider the process
P 2Pfc;c1;c2gdened as follows:
P
=
fF 2Ffc;c1;c2g jcRF(n1;'1;d1)c1;cRF(n2;'2;d2)c2g(8) (induced by a
Signalprogram that manipulates only the clocks
c,
c1and
c2).
From the denition of an ane relation associated with a process it results
c R P
(n
1
;'
1
;d
1 )
c
1
and
cRP(n2;'
2
;d
2 )
c
2
. Clocks
c1and
c2are synchronisable in
Pif there exists
F 2 Psatisfying
c1=
F c2. Consider
Fs 2 Psatisfying
c1 F=
s c2. Obviously
c RF(n1;'1;d1)s c1and
cRF(n2;'2;d2)s c2. Being identical in
Fs, clocks
c1and
c2can be replaced with each other and therefore
c RF(n1;'1;d1)s c1implies
c R F
s
(n1;'1;d1) c
2
and
cRF(n2;'2;d2)s c2implies
c RF(n2;'2;d2)s c1. It results therefore that
RFs(n1;'1;d1)=
RFs(n2;'2;d2)=
f(
c;c1)
;(
c;c2)
g. In conclusion, a necessary con- dition for clocks
c1and
c2to be synchronisable in
Pis that
RFs(n1;'1;d1)and
R F
s
(n2;'2;d2)