XContext Register (CP0 Register 20, Select 0)

Compliance Level: Required for 64-bit TLB-based MMUs. Optional otherwise.

TheXContext register is a read/write register containing a pointer to an entry in the page table entry (PTE) array.

This array is an operating system data structure that stores virtual-to-physical translations. During a TLB miss, the operating system loads the TLB with the missing translation from the PTE array. TheXContextregister is primarily intended for use with the XTLB Refill handler, but is also loaded by hardware on a TLB Refill. However, it is unlikely to be useful to software in the TLB Refill Handler. TheXContext register duplicates some of the information pro-vided in theBadVAddr register.

IfConfig3_CTXTC=0 then theXContextregister is organized in such a way that the operating system can directly ref-erence a 16-byte structure in memory that describes the mapping. For PTE structures of other sizes, the content of this register can be used by the TLB refill handler after appropriate shifting and masking.

IfConfig3_CTXTC =0 then a TLB exception (TLB Refill, XTLB Refill, TLB Invalid, or TLB Modified) causes bits 63..62 of the virtual address to be written into the R field and bits SEGBITS-1..13 of the virtual address to be written into the BadVPN2 field of theXContext register. The PTEBase field is written and used by the operating system.

The BadVPN2 and R fields of theXContext register are not defined after an address error exception and these fields may be modified by hardware during the address error exception sequence.

Figure 9-38shows the format of theXContextregister whenConfig3_CTXTC=0;Table 9.46describes theXContext register fields whenConfig3_CTXTC =0. InFigure 9-38, bit numbers above the figure use the symbol SEGBITS; bit number under the figure assume that SEGBITS has the value 40.

Figure 9-38 XContext Register Format when Config3_CTXTC=0

Table 9.46 XContext Register Fieldswhen Config3_CTXTC=0 Field

PTEBase 63 .. SEGBITS-13+6 (63..33 assuming

SEGBITS is 40)

This field is for use by the operating system and is normally written with a value that allows the operat-ing system to use theXContext Register as a pointer into the current PTE array in memory

R/W Undefined Required

IfConfig3_CTXTC=1 then the pointer implemented by theXContextregister can point to any power-of-two-sized PTE structure within memory. This allows the TLB refill handler to use the pointer without additional shifting and mask-ing steps. Dependmask-ing on the value in theXContextConfigregister, it may point to an 8-byte pair of 32-bit PTEs within a single-level page table scheme, or to a first level page directory entry in a two-level lookup scheme.

If^Config3_CTXTC=1 then the a TLB exception (Refill, Invalid, or Modified) causes bits VASEGBITS-1:SEGBITS-(X-Y)to be written to a variable range of bits “(X-1):Y” of theXContext register, where this range corresponds to the contigu-ous range of set bits in theXContextConfigregister. The exception causes bits 63..62 of the virtual address to be writ-ten into the R field. Bits 63:X+2 are R/W to software, and are unaffected by the exception. Bits Y-1:0 are unaffected by the exception. If X = 31 and Y = 4, i.e. bits 30:4 are set inXContextConfig, the behavior is identical to the standard MIPS IIIXContext register (bits 30:4 are filled with VA_39:13when SEGBITS equals 40). Although the fields have been made variable in size and interpretation, the MIPS64 nomenclature is retained. Bits 63:X are referred to as the PTEBase and R fields, and bits X-1:Y are referred to as BadVPN2.

The value of theXContext register is UNPREDICTABLE following a modification of the contents of the XContextConfig register.

Figure 9-39shows the format of theXContextRegister whenConfig3_CTXTC=1;Table 9.47describes theXContext register fieldsConfig3_CTXTC =1.

R SEGBITS-13+5 ..

SEGBITS-13+4 (32..31 assuming

SEGBITS is 40)

The Region field contains bits 63..62 of the virtual address.

For processors implementing Config_AT = 1 (access to 32-bit compatibility segments only), only the 0b00 and 0b11 values are supplied by the processor on an exception.

R Undefined Required

BadVPN2 SEGBITS-13+3 .. 4 (30..4 assuming SEGBITS is 40)

The Bad Virtual Page Number/2 field is written by hardware on a miss. It contains bits VASEGBITS-1..13of the virtual address that missed.

R Undefined Required

0 3..0 Must be written as zero; returns zero on read. 0 0 Reserved

Field

0b01 xsseg: supervisor address region. If Supervisor Mode is not imple-mented, this encoding is reserved 0b10 Reserved

0b11 xkseg

Figure 9-39 XContext Register Format when Config3_CTXTC=1

63 X+2 X+1 X X-1 Y Y-1 0

PTEBase R BadVPN2 0

Table 9.47 XContext Register Field Descriptions when Config3_CTXTC=1

Fields

This field is for use by the operating system and is normally written with a value that allows the operat-ing system to use theContextRegister as a pointer to an array of data structures in memory corresponding to the address region containing the virtual address which caused the exception.

R/W Undefined Required

R X+1:X

where X in {63..0}.

May be null.

The Region field contains bits 63..62 of the virtual address.

For processors implementing Config_AT = 1 (access to 32-bit compatibility segments only), only the 0b00 and 0b11 values are supplied by the processor on an exception.

This field is written by hardware on a TLB exception.

It contains bits VASEGBITS-1:SEGBITS-(X-Y) of the virtual address that caused the exception.

R Undefined Required

0 Variable, (Y-1):0 where

Y in {63:1}.

May be null.

Must be written as zero; returns zero on read. 0 0 Reserved

Encoding Meaning

0b00 xuseg

0b01 xsseg: supervisor address region. If Supervisor Mode is not imple-mented, this encoding is reserved 0b10 Reserved

0b11 xkseg

Compliance Level: Implementation Dependent.

CP0 register 22 is reserved for implementation dependent use and is not defined by the architecture.