EntryHi Register (CP0 Register 10, Select 0)

Compliance Level: Required for TLB-based MMU; Optional otherwise.

TheEntryHi register contains the virtual address match information used for TLB read, write, and access operations.

A TLB exception (TLB Refill, XTLB Refill, TLB Invalid, or TLB Modified) causes the bits of the virtual address cor-responding to the R and VPN2 fields to be written into theEntryHi register. An implementation of Release 2 of the Architecture which supports 1KB pages also writes VA_12..11 into the VPN2X field of theEntryHi register. A TLBR instruction writes theEntryHi register with the corresponding fields from the selected TLB entry. The ASID field is written by software with the current address space identifier value and is used during the TLB comparison process to determine TLB match.

Because the ASID field is overwritten by a TLBR instruction, software must save and restore the value of ASID around use of the TLBR. This is especially important in TLB Invalid and TLB Modified exceptions, and in other memory management software.

Software may determine the value of SEGBITS by writing all ones to theEntryHiregister and reading the value back.

Bits read as “1” from the VPN2 field allow software to determine the boundary between the VPN2 and Fill fields to calculate the value of SEGBITS.

The VPNX2, VPN2, and R fields of theEntryHi register are not defined after an address error exception and these fields may be modified by hardware during the address error exception sequence. Software writes of theEntryHi reg-ister (via MTC0 or DMTC0) do not cause the implicit write of address-related fields in theBadVAddr,Context, or XContext registers.

Figure 9-19 shows the format of theEntryHi register;Table 9.24 describes theEntryHi register fields.

Figure 9-19 EntryHi Register Format

63 62 61 40 39 32

R Fill VPN2

VPN2, cont. VPN2X 0 ASID

31 13 12 11 10 8 7 0

Fields

R 63..62 Virtual memory region, corresponding to VA_63..62.

This field is written by hardware on a TLB exception or on a TLB read, and is written by software before a TLB write.

For processors implementing Config_AT = 1 (access to 32-bit compatibility segments only), only the 0b00 and 0b11 values are legal. In this circumstance, the operation of the processor is UNDEFINED if EntryHi_R is written with any other value, and the processor will only supply the legal values on an exception.

R/W Undefined Required

Fill 61..40 Fill bits reserved for expansion of the virtual address space. See below. Returns zeros on read, ignored on write.

R 0 Required

VPN2 39..13 VA_39..13of the virtual address (virtual page number / 2).

This field is written by hardware on a TLB exception or on a TLB read, and is written by software before a TLB write. The default width of this field implicitly limits the size of each virtual address space to 40 bits. If the pro-cessor implements fewer virtual address bits than this default, the Fill field must be extended to take up the unimplemented VPN2 bits. If the processor implements more virtual address bits than this default, the VPN2 field must be extended to take up some or all of the Fill bits.

R/W Undefined Required

VPN2X 12..11 In Release 2 of the Architecture (and subsequent releases), the VPN2X field is an extension to the VPN2 field to support 1KB pages. These bits are not writable by either hardware or software unless Config3_SP= 1 and PageGrain_ESP = 1. If enabled for write, this field con-tains VA_12..11 of the virtual address and is written by hardware on a TLB exception or on a TLB read, and is by software before a TLB write.

If writes are not enabled, and in implementations of Release 1 of the Architecture, this field must be written with zero and returns zeros on read.

R/W 0 Required

(Release 2 and 1KB Page

Sup-port)

0 10..8 Must be written as zero; returns zero on read. 0 0 Reserved

Encoding Meaning

0b00 xuseg: user address region 0b01 xsseg: supervisor address region. If

Supervisor Mode is not implemented, this encoding is reserved

0b10 Reserved

0b11 xkseg: kernel address region

Programming Note:

In implementations of Release 2 (and subsequent releases) of the Architecture, the VPN2X field of theEntryHi regis-ter must be written with zero and the TLB must be flushed before each instance in which the value of thePageGrain register is changed. This operation must be carried out while running in an unmapped address space. The operation of the processor is UNDEFINED if this sequence is not done.

ASID 7..0 Address space identifier. This field is written by hard-ware on a TLB read and by softhard-ware to establish the cur-rent ASID value for TLB write and against which TLB references match each entry’s TLB ASID field.

R/W Undefined Required (TLB MMU)

Table 9.24 EntryHi Register Field Descriptions

Fields

Description

Read / Write

Reset

State Compliance

Name Bits

Compliance Level: Required.

TheCompareregister acts in conjunction with theCountregister to implement a timer and timer interrupt function.

TheCompare register maintains a stable value and does not change on its own.

When the value of theCount register equals the value of theCompare register, an interrupt request is made. In Release 1 of the architecture, this request is combined in an implementation-dependent way with hardware interrupt 5 to set interrupt bit IP(7) in theCause register. In Release 2 (and subsequent releases) of the Architecture, the pres-ence of the interrupt is visible to software via the Cause_TI bit and is combined in an implementation-dependent way with a hardware or software interrupt. For Vectored Interrupt Mode, the interrupt is at the level specified by the IntCtl_IPTI field.

For diagnostic purposes, theCompareregister is a read/write register. In normal use however, theCompareregister is write-only. Writing a value to theCompare register, as a side effect, clears the timer interrupt.Figure 9-20 shows the format of theCompare register;Table 9.25 describes theCompare register fields.

Programming Note:

In Release 2 of the Architecture, the EHB instruction can be used to make interrupt state changes visible when the Compareregister is written. See6.1.2.1 “Software Hazards and the Interrupt System” on page 58.