GPR Shadow Registers
9.5 Random Register (CP0 Register 1, Select 0)
Compliance Level: Required for TLB-based MMUs; Optional otherwise.
TheRandomregister is a read-only register whose value is used to index the TLB during a TLBWR instruction. The width of the Random field is calculated in the same manner as that described for theIndex register above.
The value of the register varies between an upper and lower bound as follow:
• A lower bound is set by the number of TLB entries reserved for exclusive use by the operating system (the con-tents of theWiredregister). The entry indexed by theWiredregister is the first entry available to be written by a TLB Write Random operation.
• An upper bound is set by the total number of TLB entries minus 1.
Within the required constraints of the upper and lower bounds, the manner in which the processor selects values for theRandom register is implementation-dependent.
The processor initializes theRandomregister to the upper bound on a Reset Exception, and when theWiredregister is written.
Figure 9-2 shows the format of theRandom register;Table 9.4 describes theRandom register fields.
Figure 9-2 Random Register Format
31 n n-1 0
0 Random
Table 9.4 Random Register Field Descriptions
Fields
Description
Read/
Write Reset State Compliance
Name Bits
0 31..n Must be written as zero; returns zero on read. 0 0 Reserved
Random n-1..0 TLB Random Index R TLB Entries - 1 Required
Compliance Level:EntryLo0 is Required for a TLB-based MMU; Optional otherwise.
Compliance Level:EntryLo1 is Required for a TLB-based MMU; Optional otherwise.
The pair ofEntryLo registers act as the interface between the TLB and the TLBP, TLBR, TLBWI, and TLBWR instructions.EntryLo0 holds the entries for even pages andEntryLo1 holds the entries for odd pages.
Software may determine the value of PABITS by writing all ones to theEntryLo0orEntryLo1registers and reading the value back. Bits read as “1” from the PFN field allow software to determine the boundary between the PFN/PFNX and Fillfields to calculate the value of PABITS.
The contents of theEntryLo0andEntryLo1registers are not defined after an address error exception and some fields may be modified by hardware during the address error exception sequence. Software writes of theEntryHi register (via MTC0 or DMTC0) do not cause the implicit update of address-related fields in theBadVAddrorContext regis-ters.
For Release 1 of the Architecture,Figure 9-3 shows the format of theEntryLo0 andEntryLo1 registers;Table 9.5 describes theEntryLo0 andEntryLo1 register fields.
For Release 2 of the Architecture,Figure 9-4 shows the format of theEntryLo0 andEntryLo1 registers;Table 9.6 describes theEntryLo0 andEntryLo1 register fields.
For Release 3 of the Architecture,Figure 9-5 shows the format of theEntryLo0 andEntryLo1 registers;Figure 9.7 describes theEntryLo0 andEntryLo1 register fields.
Figure 9-3 EntryLo0, EntryLo1 Register Format in Release 1 of the Architecture
63 32
Fill
Fill PFN C D V G
31 30 29 6 5 3 2 1 0
Table 9.5 EntryLo0, EntryLo1 Register Field Descriptions in Release 1 of the Architecture
Fields
Description
Read /
Write Reset State Compliance
Name Bits
Fill 63..30 These bits are ignored on write and return zero on read.
The boundaries of this field change as a function of the value of PABITS. SeeTable 9.8 for more information.
R 0 Required
PFN 29..6 Page Frame Number. Corresponds to bits PABITS-1..12 of the physical address, where PABITS is the width of the physical address in bits. The boundaries of this field change as a function of the value of PABITS. SeeTable 9.8 for more information.
R/W Undefined Required
C 5..3 Cacheability and Coherency Attribute of the page. See Table 9.9 below.
R/W Undefined Required
D 2 “Dirty” bit, indicating that the page is writable. If this bit is a one, stores to the page are permitted. If this bit is a zero, stores to the page cause a TLB Modified exception.
Kernel software may use this bit to implement paging algorithms that require knowing which pages have been written. If this bit is always zero when a page is initially mapped, the TLB Modified exception that results on any store to the page can be used to update kernel data struc-tures that indicate that the page was actually written.
R/W Undefined Required
V 1 Valid bit, indicating that the TLB entry, and thus the vir-tual page mapping are valid. If this bit is a one, accesses to the page are permitted. If this bit is a zero, accesses to the page cause a TLB Invalid exception.
R/W Undefined Required
G 0 Global bit. On a TLB write, the logical AND of the G bits from bothEntryLo0 andEntryLo1 becomes the G bit in the TLB entry. If the TLB entry G bit is a one, ASID comparisons are ignored during TLB matches. On a read from a TLB entry, the G bits of bothEntryLo0 andEntryLo1 reflect the state of the TLB G bit.
R/W Undefined Required (TLB
MMU)
Figure 9-4 EntryLo0, EntryLo1 Register Format in Release 2 of the Architecture
63 55 54 32
Fill PFNX
PFNX PFN C D V G
31 30 29 6 5 3 2 1 0
Table 9.6 EntryLo0, EntryLo1 Register Field Descriptions in Release 2 of the Architecture
Fields
Description
Read /
Write Reset State Compliance
Name Bits
Fill 63..55 These bits are ignored on write and return zero on read.
The boundaries of this field change as a function of the value of PABITS. SeeTable 9.8 for more information.
R 0 Required
Table 9.5 EntryLo0, EntryLo1 Register Field Descriptions in Release 1 of the Architecture
Fields
Description
Read /
Write Reset State Compliance
Name Bits
PFNX 54..30 Page Frame Number Extension. If the processor is enabled to support large physical addresses (Config3LPA
= 1 and PageGrainELPA = 1), this field is concatenated with the PFN field to form the full page frame number corresponding to the physical address, thereby providing up to 59 bits of physical address.
If the processor is enabled to support 1KB pages (Config3SP = 1 and PageGrainESP = 1), the combined PFNX|| PFN fields corresponds to bits PABITS-1..10 of the physical address (the field is shifted left by 2 bits relative to the Release 1 definition to make room for PA11..10).
If the processor is not enabled to support 1KB pages (Config3SP = 0 or PageGrainESP = 0), the combined PFNX|| PFN fields corresponds to 0b00||bits PABITS-1..12 of the physical address (the field is unshifted and the upper two bits must be written as zero).
The boundaries of this field change as a function of the value of PABITS. SeeTable 9.8 for more information.
If support for large physical addresses is not enabled (Config3LPA = 0 or PageGrainELPA = 0), these bits are ignored on write and return 0 on read, thereby providing full backward compatibility with implementations of Release 1 of the Architecture.
R/W 0 Optional
PFN 29..6 Page Frame Number. This field contains least-significant bits of the physical page number corresponding to the virtual page. If the processor is enabled to support large physical addresses, the PFNX field, described above is concatenated with the PFN field to form the full page frame number. If the processor is not enabled to support large physical addresses, the entire page frame number is represented by this field. See the description of the PFNX field above for more information.
If the processor is enabled to support 1KB pages (Config3SP = 1 and PageGrainESP = 1), the PFN field corresponds to bits 33..10 of the physical address (the field is shifted left by 2 bits relative to the Release 1 def-inition to make room for PA11..10).
If the processor is not enabled to support 1KB pages (Config3SP = 0 or PageGrainESP = 0), the PFN field cor-responds to bits 35..12 of the physical address.
The boundaries of this field change as a function of the value of PABITS. SeeTable 9.8 for more information.
R/W Undefined Required
C 5..3 The definition of this field is unchanged from Release 1.
SeeTable 9.5 above andTable 9.9 below.
R/W Undefined Required
D 2 The definition of this field is unchanged from Release 1.
SeeTable 9.5 above.
R/W Undefined Required
Fields
Description
Read /
Write Reset State Compliance
Name Bits
V 1 The definition of this field is unchanged from Release 1.
SeeTable 9.5 above.
R/W Undefined Required
G 0 The definition of this field is unchanged from Release 1.
SeeTable 9.5 above.
R/W Undefined Required (TLB MMU)
Figure 9-5 EntryLo0, EntryLo1 Register Format in Release 3 of the Architecture
63 62 61 55 54 32
RI XI Fill PFNX
PFNX PFN C D V G
31 30 29 6 5 3 2 1 0
Table 9.7 EntryLo0, EntryLo1 Register Field Descriptions in Release 3 of the Architecture
Fields
Description
Read /
Write Reset State Compliance
Name Bits
Fill 61..55 These bits are ignored on write and return zero on read.
The boundaries of this field change as a function of the value of PABITS. SeeTable 9.8 for more information.
R 0 Required if RI
and XI fields are not
imple-mented.
RI 63 Read Inhibit. If this bit is set in a TLB entry, an attempt, other than a MIPS16 PC-relative load, to read data on the virtual page causes a TLB Invalid or a TLBRI excep-tion, even if the V (Valid) bit is set. The RI bit is writable only if the RIE bit of thePageGrainregister is set. If the RIE bit ofPageGrain is not set, the RI bit of
EntryLo0/EntryLo1 is set to zero on any write to the register, regardless of the value written.
This bit is optional and its existence is denoted by the Config3RXI orConfig3 SMregister fields.
R/W 0 Required by
SmartMIPS of the Fill field.
XI 62 Execute Inhibit. If this bit is set in a TLB entry, an attempt to fetch an instruction or to load MIPS16 PC-rel-ative data from the virtual page causes a TLB Invalid or a TLBXI exception, even if the V (Valid) bit is set. The XI bit is writable only if the XIE bit of thePageGrain register is set. If the XIE bit ofPageGrainis not set, the XI bit ofEntryLo0/EntryLo1is set to zero on any write to the register, regardless of the value written.
This bit is optional and its existence is denoted by the Config3RXI orConfig3 SMregister fields.
R/W 0 Required by
SmartMIPS of the Fill field.
Table 9.6 EntryLo0, EntryLo1 Register Field Descriptions in Release 2 of the Architecture
Fields
Description
Read /
Write Reset State Compliance
Name Bits
PFNX 54..30 Page Frame Number Extension. If the processor is enabled to support large physical addresses (Config3LPA
= 1 and PageGrainELPA = 1), this field is concatenated with the PFN field to form the full page frame number corresponding to the physical address, thereby providing up to 59 bits of physical address.
If the processor is enabled to support 1KB pages (Config3SP = 1 and PageGrainESP = 1), the combined PFNX|| PFN fields corresponds to bits PABITS-1..10 of the physical address (the field is shifted left by 2 bits relative to the Release 1 definition to make room for PA11..10).
If the processor is not enabled to support 1KB pages (Config3SP = 0 or PageGrainESP = 0), the combined PFNX|| PFN fields corresponds to 0b00||bits PABITS-1..12 of the physical address (the field is unshifted and the upper two bits must be written as zero).
The boundaries of this field change as a function of the value of PABITS. SeeTable 9.8 for more information.
If support for large physical addresses is not enabled (Config3LPA = 0 or PageGrainELPA = 0), these bits are ignored on write and return 0 on read, thereby providing full backward compatibility with implementations of Release 1 of the Architecture.
R/W 0 Optional
PFN 29..6 Page Frame Number. This field contains least-significant bits of the physical page number corresponding to the virtual page. If the processor is enabled to support large physical addresses, the PFNX field, described above is concatenated with the PFN field to form the full page frame number. If the processor is not enabled to support large physical addresses, the entire page frame number is represented by this field. See the description of the PFNX field above for more information.
If the processor is enabled to support 1KB pages (Config3SP = 1 and PageGrainESP = 1), the PFN field corresponds to bits 33..10 of the physical address (the field is shifted left by 2 bits relative to the Release 1 def-inition to make room for PA11..10).
If the processor is not enabled to support 1KB pages (Config3SP = 0 or PageGrainESP = 0), the PFN field cor-responds to bits 35..12 of the physical address.
The boundaries of this field change as a function of the value of PABITS. SeeTable 9.8 for more information.
R/W Undefined Required
C 5..3 The definition of this field is unchanged from Release 1.
SeeTable 9.5 above andTable 9.9 below.
R/W Undefined Required
D 2 The definition of this field is unchanged from Release 1.
SeeTable 9.5 above.
R/W Undefined Required
Fields
Description
Read /
Write Reset State Compliance
Name Bits
Table 9.8shows the movement of the Fill, PFNX, and PFN fields as a function of 1KB page support enabled, and the value of PABITS. Note that in implementations of Release 1 of the Architecture, PABITS can never be larger than 36 bits and there is no support for 1KB pages, so only the second row of the table applies to Release 1.
Programming Note:
In implementations of Release 2 of the Architecture (and subsequent releases), the PFNX and PFN fields of both the EntryLo0andEntryLo1registers must be written with zero and the TLB must be flushed before each instance in which the value of the PageGrain register is changed. This operation must be carried out while running in an unmapped address space. The operation of the processor is UNDEFINED if this sequence is not done.
Table 9.9lists the encoding of the C field of theEntryLo0andEntryLo1registers and the K0 field of theConfig reg-ister. An implementation may choose to implement a subset of the cache coherency attributes shown, but must imple-V 1 The definition of this field is unchanged from Release 1.
SeeTable 9.5 above.
R/W Undefined Required
G 0 The definition of this field is unchanged from Release 1.
SeeTable 9.5 above.
R/W Undefined Required (TLB MMU)
Table 9.8 EntryLo Field Widths as a Function of PABITS
1KB Page Support
Enabled? PABITS Value
Corresponding EntryLo Field Bit Ranges
Release 2 Required?
Fill Field PFNX Field PFN Field
No 59≥PABITS > 36 63..(53-(59-PABITS)) Example:
36≥PABITS > 12 63..(30-(36-PABITS)) Example:
63..30 if PABITS = 36 63..7 if PABITS = 13
Displaced by the Fill Field
Yes 59≥PABITS > 34 63..(55-(59-PABITS)) Example:
34≥PABITS > 10 63..(30-(34-PABITS)) Example:
63..30 if PABITS = 34 63..7 if PABITS = 11
Displaced by the Fill Field
Table 9.7 EntryLo0, EntryLo1 Register Field Descriptions in Release 3 of the Architecture
Fields
Description
Read /
Write Reset State Compliance
Name Bits
fetch or for a load/store instruction) which was created with a C field encoding which is RESERVED for the imple-mentation.
Table 9.9 lists the required and optional encodings for the cacheability and coherency attributes.
Table 9.9 Cacheability and Coherency Attributes
C(5:3) Value
Cacheability and Coherency Attributes
With Historical Usage Compliance
0 Available for implementation dependent use Optional
1 Available for implementation dependent use Optional
2 Uncached Required
3 • Cacheable Required
4 Available for implementation dependent use Optional
5 Available for implementation dependent use Optional
6 Available for implementation dependent use Optional
7 Available for implementation dependent use Optional