TRUTH TABLE (NOTE 1) (NOTE 1)

oAo DBo

TRUTH TABLE (NOTE 1) (NOTE 1)

INPUTS

OE

L L H NOTE:

1. H

=

HIGH Voltage Level L

=

LOW Voltage Level X= Don't Care Z

=

High Impedance

TIR L H X

Pin Descriptions

PIN NAME DESCRIPTION

OE

Three-State Output Enable Inputs (Active LOW)

TIR Direction Control Input

A7-Ao Side A Inputs or Three-State Outputs B7-BO Side B Inputs or Three-State Outputs

GND Ground

Vee Power

(NOTE 1) OUTPUTS Bus B Data to Bus A Bus A Data to Bus B High Z State

3-86

CD74LPT245

Absolute Maximum Ratings

Thermal Information

DC Input Voltage ... , ... , . -0.5V to 7.0V Thermal Resistance (Typical, Note 2) 9JA (oCIW) DC Output Current ... 120mA SOIC Package. . . . 87

asop

Package. . . 110 Operating Conditions Maximum Junction Temperature ... 150°C Operating Temperature Range ... -40°C to 85°C Maximum Storage Temperature Range ... -65⁰C to 150°C Supply Voltage to Ground Potential Maximum Lead Temperature (Soldering 1 Os) ... 300°C

Inputs and Vee Only ... -0.5V to 7.0V (Lead Tips Only) Supply Voltage to Ground Potential

Outputs and % Only ... , ... , . -0.5V to 7.0V

CAUTION: Stresses above those listed in "Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated In the operational sections of this speCification is not implied.

NOTE:

2. 8JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

(NOTE 3) (NOTE 4)

PARAMETER SYMBOL TEST CONDITIONS MIN

TYP

MAX UNITS

DC ELECTRICAL SPECIFICATIONS Over the Operating Range, TA = -40°C to 85°C, Vee = 2.7V to 3.6V

Input HIGH Voltage VIH Guaranteed Logic HIGH Level 2.2 5.5 V

(Input Pins)

Input HIGH Voltage VIH Guaranteed Logic HIGH Level 2.0 5.5 V

(I/O Pins)

Input LOW Voltage VIL Guaranteed Logic LOW Level -0.5 0.8 V

(Input and I/O Pins)

Input HIGH Current IIH Vee = Max VIN =5.5V ±1

I1A

(Input Pins)

Input HIGH Current IIH Vee = Max VIN=Vee ±1

I1A

(I/O Pins)

Input LOW Current IlL Vee = Max VIN=GND ±1

I1A

(Input Pins)

Input LOW Current IlL Vee = Max VIN=GND ±1

I1A

(I/O Pins)

High Impedance IOZH Vee = Max VOUT= 5.5V

-

^±1

I1A

Output Current

(Three-State) IOZL Vee = Max VOUT=GND ±1

I1A

Clamp Diode Voltage VIK Vee = Min, liN = -18mA -0.7 -1.2 V

Output HIGH Current IOOH Vee = 3.3V, VIN = VIH or VIL, Vo = 1.5V (Note 5) -36 -60 -110 mA Output LOW Current IOOL Vee = 3.3V, VIN = VIH or VIL, Vo = 1.5V (Note 5) 50 90 200 mA Output HIGH Voltage VOH Vee = Min, VIN = VIH or VIL IOH = -0.1mA Vee- 0.2

-

IOH=-3mA 2.4 3.0

-

Vee

=

3.0V, VIN

=

VIH or VIL IOH=-8mA 2.4 3.0

-

(Note 7)

IOH=-24mA 2.0 V

Output LOW Voltage VOL Vee = Min, VIN = VIH orVIL IOL = 0.1mA

-

^0.2 ^V

IOL = 16mA 0.2 0.4 V

IOL=24mA 0.3 0.5 V

3-87

Electrical Specifications

(Continued)

(NOTE 3) (NOTE 4)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Short Circuit Current los Vee = Max (Note 5), VOUT = GND -60 -85 -240 rnA

(Note 6)

Power Down Disable 10FF Vee = OV, VIN or VOUTS 4.5V ±100 J.LA

Input Hysteresis VH 150 rnV

CAPACITANCE TA = 25°C, f = 1 MHz

Input Capacitance CIN VIN=OV

-

^4.5 ⁶ ^pF

(Note 8)

Output Capacitance COUT VOUT=OV 5.5 8 pF

(Note 8)

POWER SUPPLY SPECIFICATIONS

Quiescent Power lee Vee = Max VIN=GND 0.1 10 J.LA

Supply Current or Vee

Quiescent Power Alee Vee = Max VIN = VCC - 0.6V

-

^2.0 ³⁰ J.LA

Supply Current TTL (Note 9)

Inputs HIGH

Dynamic Power leeD Vee = Max, Outputs Open VIN=Vee 50 75

J.LAI

Supply Current OE=GND VIN=GND MHz

(Note 10) One Bit Toggling

50% Duty Cycle

Total Power Supply Ie Vee:;: Max, Outputs Open VIN = Vee - 0.6V 0.6 2.3 mA Current (Note 12) fl = 10MHz, 50% Duty Cycle VIN=GND

OE=GND One Bit Toggling

Vee = Max, Outputs Open VIN = Vee - 0.6V 2.1 4.7 mA

fl = 2.5MHz, 50% Duty Cycle VIN=GND (Note 11)

OE=GND 8 Bits Toggling

3-88

CD74LPT245 Switching Specifications Over Operating Range

(NOTE 13)

(NOTE 14) CD74LPT245 CD74LPT245A CD74LPT245C TEST (NOTE 15) (NOTE 15) (NOTE 15)

PARAMETER SYMBOL CONDITIONS MIN MAX MIN MAX MIN MAX UNITS

Propagation Delay tpLH, CL = 50pF 1.5 7.0 1.5 4.6 1.5 4.1 ns

AtoB, BtoA tpHL RL=500n

Output Enable Time tpZH, 1.5 8.5 1.5 6.2 1.5 5.8 ns

OEtoAorB tPZL

Output Disable Time tPHZ, 1.5 7.5 1.5 5.0 1.5 4.8 ns

OE to A or B (Note 16) tpLZ

Output Enable Time tpZH, 1.5 8.5 1.5 6.2 1.5 5.8 ns

T/RtoAorB tPZL

Output Disable Time tpHZ, 1.5 7.5 1.5 5.0 1.5 4.8 ns

T/R to A or B (Note 16) tpLZ

Output Skew (Note 17) _tSK(O~

-

^0.5 ^0.5 ^0.5 ^ns

NOTES:

3. For conditions shown as Max or Min, use appropriate value specified under Electrical Specifications for the applicable device type.

4. Typical values are at VCC = 3.3V, 25°C ambient and maximum loading.

5. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.

6. This parameter is guaranteed but not tested.

7. VOH

=

VCC - 0.6V at rated current.

8. This parameter is determined by device characterization but is not production tested.

9. Per TTL driven input; all other inputs at VCC or GND.

10. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.

11. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.

12. IC = laUIESCENT

+

IINPUTS

+

IDYNAMIC IC = Icc + AICC DHNT + ICCD (fcp/2 + flNI) Icc = Quiescent Current

AICC = Power Supply Current for a TTL High Input DH = Duty Cycle for TTL Inputs High

NT = Number of TTL Inputs at DH

ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices) fl = Input Frequency

NI = Number of Inputs at fl

All currents are in milliamps and all frequencies are in megahertz.

13. Propagation Delays and Enable/Disable times are with VCC = 3.3V ±O.3V, normal range. For Vcc = 2.7V, extended range, all Propaga-tion Delays and Enable/Disable times should be degraded by 20%.

14. See test circuit and wave forms.

15. Minimum limits are guaranteed but not tested on Propagation Delays.

16. This parameter is guaranteed but not production tested.

17. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.

3-89

Test Circuits and Waveforms Vee

NOTE:

8V OPEN

-!-GND

soon

18. Pulse Generator for All Pulses: Rate ~ 1.0MHz; loUT ~

son;

tf. tr ~ 2.5ns.

FIGURE 1. TEST CIRCUIT

CONTROL INPUT

OUTPUT NORMALLY LOW

OUTPUT NORMALLY HIGH

FIGURE 2. ENABLE AND DISABLE TIMING

3-90

SWITCH POSITION

TEST SWITCH

tpLZ. tpZL. Open Drain 6V

tpHZ. tPZH GND

tpLH. tpHL Open

DEFINITIONS:

=

Load capacitance. includes jig and probe capacitance.

=

Termination resistance. should be equal to loUT of the Pulse Generator.

SAME PHASE INPUT TRANsmON

OUTPUT

OPPOSITE PHASE INPUT TRANSmON

, . - - , , - ; - - - 3V + - - - 1 . 5 V

' - - - O V

~-.... ..n--VOH -1.5V ----1t-J'o-VOL

~""--3V - # - - - - 1 . 5 V

"""'--"'" - - - - O V FIGURE 3. PROPAGATION DELAY

CD74LPT373

December 1996

Fast CMOS 3.3V 8-Bit Transparent Latch

Features Description

• Advanced 0.6 micron CMOS Technology

• Compatible with LCXTM Families of Products

• Supports 5V Tolerant Mixed Signal Mode Operation - Input Can Be 3V or 5V

The CD74LPT373 is an a-bit transparent latch designed with three-state outputs and is intended for bus oriented applica-tions. When Latch Enable (LE) is HIGH, the flip-flops appear transparent to the data. The data that meets the set-up time when LE is LOW is latched. When OE is HIGH, the bus out-put is in the high impedance state.

- Output Can Be 3V or Connected to 5V Bus

• Advanced Low Power CMOS Operation

• Exce"ent Output Drive Capability:

The CD74LPT373 can be driven from either 3.3V or 5.0V devices allowing this device to be used as a translator in a mixed 3.3/5.0V system.

- Balanced Drives (24mA Sink and Source)

• Low Ground Bounce Outputs

• Hysteresis on A" Inputs

Ordering Information

TEMP.

RANGE PKG.

PART NUMBER

fc)

PACKAGE NO.

CD74LPT373AM -40 to 85 20 LdSOIC M20.3-P CD74LPT373AQM -40 to 85 20 LdQSOP M20.15-P CD74LPT373CM -40 to 85 20 LdSOIC M20.3-P CD74LPT373CQM -40 to 85 20 LdQSOP M20.15-P CD74LPT373M -40 to 85 20 LdSOIC M20.3-P CD74LPT373QM -40 to 85 20 LdQSOP M20.15-P NOTE: QSOP is commonly known as SSO?

When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel.

Pinout

CD74LPT373 (QSOP, SOIC) TOP VIEW

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

3-91

File Number

4199.1

Functional Block Diagram

TRUTH TABLE (NOTE 1) INPUTS

ON H L X NOTE:

1. H

=

High Voltage Level L = Low Voltage Level X

=

Don't Care Z

=

High Impedance

Pin Descriptions

PIN NAME DESCRIPTION

DE

Output Enable Input (Active LOW) LE Latch Enable Input (Active HIGH)

°7-00 Data Inputs 07-00 Three-State Outputs

GND Ground

Vee Power

LE OE

H L

X H

3-92

OUTPUTS ON

H L Z

CD74LPT373

Absolute Maximum Ratings

Thermal Information

DC Input Voltage ... -0.5V to 7.0V Thermal Resistance (Typical, Note 2) 9JA fCIW) DC Output Current ... 120mA SOIC Package. . . 87

asop

Package. . . 110 Operating Conditions Maximum Junction Temperature ... 150°C Operating Temperature Range ... -40°C to 85°C Maximum Storage Temperature Range ... , .... -65⁰C to 150°C Supply Voltage to Ground Potential Maximum Lead Temperature (Soldering 10s) ... 300°C

Inputs and Vee Only ... -0.5V to 7.0V (Lead Tips Only) Supply Voltage to Ground Potential

Outputs and D/O Only ... -0.5V to 7.0V

CAUTION: Stresses above those listed in "Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not Implied.

NOTE:

2. 9JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

(NOTE 3) (NOTE 4)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

DC ELECTRICAL SPECIFICATIONS Over the Operating Range, TA = -40°C to 85°C, Vee = 2.7V to 3.6V

Input HIGH Voltage VIH Guaranteed Logic HIGH Level 2.2 5.5 V

(Input Pins)

Input HIGH Voltage VIH Guaranteed Logic HIGH Level 2.0 5.5 V

(I/O Pins)

Input LOW Voltage VIL Guaranteed Logic LOW Level -0.5

-

^0.8 ^V

(Input and I/O Pins)

Input HIGH Current IIH Vee = Max VIN=5.5V ±1

J1A

(Input Pins)

Input HIGH Current IIH Vee = Max VIN=Vee ±1

J1A

(I/O Pins)

Input LOW Current IlL Vee = Max VIN=GND ±1

J1A

(Input Pins)

Input LOW Current IlL Vee = Max VIN=GND ±1

J1A

(I/O Pins)

High Impedance IOZH Vee = Max VOUT=5.5V ±1

J1A

Output Current

(Three-State) IOZl Vee = Max VOUT=GND ±1

J1A

Clamp Diode Voltage VIK Vee = Min, liN = -18mA -0.7 -1.2 V

Output HIGH Current IOOH Vee = 3.3V, VIN = VIH or VIL, Vo = 1.5V (Note 5) -36 -60 -110 mA Output LOW Current IOOl Vee = 3.3V, VIN = VIH or VIL, Vo = 1.5V (Note 5) 50 90 200 mA

Output HIGH Voltage VOH Vee = Min, VIN = VIH orVll IOH=-0.1mA Vee - 0.2 V

IOH=-3mA 2.4 3.0 V

Vee = 3.0V, VIN = VIH orVll IOH=-8mA 2.4 3.0 V

(Note 7)

IOH=-24mA 2.0 V

Output LOW Voltage VOL Vee = Min, VIN = VIH or VIL IOL=0.1mA 0.2 V

IOL= 16mA 0.2 0.4 V

IOl=24mA 0.3 0.5 V

3-93

Electrical Specifications

(Continued)

(NOTE 3) (NOTE 4)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Short Circuit Current lOS Vee = Max (Note 5), VOUT = GND ·60 ·85 ·240 mA (Note 6)

Power Down Disable _10FF Vee = OV, VIN or VOUT S 4.SV

.

_±100 _~

Input Hysteresis VH 1S0 mV

CAPACITANCE TA = 2SoC, 1= 1MHz

Input Capacitance CIN VIN=OV 4.5 6 pF

(Note 8)

Output Capacitance COUT VOUT=OV

.

_5.S ₈ _pF

(Note 8)

POWER SUPPLY SPECIFICATIONS

Quiescent Power ICC Vee = Max VIN=GND 0.1 10 _~

Supply Current or Vee

Quiescent Power ~Iee Vee = Max VIN = VCC • 0.6V 2.0 30 _~

Supply Current TTL (Note 9)

Inputs HIGH

Dynamic Power IceD Vee = Max, outputs Open VIN=Vee

so

!lAI

Supply t5E=GND VIN=GND MHz

(Note 10) One Bit Toggling

SO% Duty Cycle

Total Power Supply Ie Vee = Max, Outputs Open VIN = Vee· 0.6V 0.6 2.3 mA Current (Note 12) 11 = 10MHz, SO% Duty Cycle VIN =GND

OE=GND One Bit Toggling

Vee = Max, Outputs Open VIN = Vee· 0.6V 2.1 4.7 mA

fl = 2.SMHz, SO% Duty Cycle VIN=GND (Note 11)

OE=GND 8 Bits Toggling

3·94

CD74LPT373 SWitching Specifications Over Operating Range

(Note 13)

CD74LPT373 CD74LPT373A CD74LPT373C (NOTE 14)

TEST (NOTE 15) (NOTE 15) (NOTE 15)

PARAMETER SYMBOL CONDITIONS MIN MAX MIN MAX MIN MAX UNITS

Propagation Delay tpLH, CL=50pF 1.5 8.0 1.5 5.2 1.5 4.2 ns

Ox to Ox tpHL RL= 500n

Propagation Delay tpLH, 2.0 8.5 2.0 8.5 2.0 5.5 ns

LEtoOx tpHL

Output Enable Time tpZH, 1.5 8.5 1.5 6.5 1.5 5.5 ns

~toOx tpZL

Output Disable Time tpHZ, 1.5 7.5 1.5 5.5 1.5 5.0 ns

(Note 16) tpLZ

OEtoOx

Setup Time HIGH or tsu 2.0

-

^2.0

-

^2.0

-

^ns

LOW, Ox to LE

Hold Time HIGH or tH 1.5 1.5

-

^1.5

-

^ns

LOW, DxtoLE

LE Pulse Width tw 6.0 5.0 5.0

-

^ns

(Note 16) HIGH

Output Skew (Note 17) tSK(O)

-

^0.5 ^0.5 ^0.5 ^ns

NOTES:

3. For conditions shown as Max or Min, use appropriate value specified under Electrical Specifications for the applicable device type.

4. Typical values are at V CC = 3.3V, 25°C ambient and maximum loading.

5. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.

6. This parameter is guaranteed but not tested.

7. VOH = VCC - 0.6V at rated current.

8. This parameter is determined by device characterization but is not production tested.

9. Per TIL driven input; all other inputs at Vcc or GND.

10. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.

11. Values for these conditions are examples of the IcC formula. These limits are guaranteed but not tested.

12. Ic = 'aUIEScENT + I,NPUTS + IDYNAMIC Ic = Icc + dlCC DHNT + ICCD (fcP/2 + fIN,) Icc = Quiescent Current

dlCC = Power Supply Current for a TIL High Input DH = Duty Cycle for TIL Inputs High

NT = Number of TIL Inputs at DH

ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices) f, = Input Frequency

N, = Number of Inputs at f,

All currents are in milliamps and all frequencies are in megahertz.

13. Propagation Delays and EnablelDisable times are with Vcc = 3.3V ±a.3V, normal range. For VCC = 2.7V, extended range, all Propaga-tion Delays and Enable/Disable times should be degraded by 20%.

14. See test circuit and wave forms.

15. Minimum limits are guaranteed but not tested on Propagation Delays.

16. This parameter is guaranteed but not production tested.

17. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.

3-95

Test Circuits and Waveforms

FIGURE 1. TEST CIRCUIT

- ~~~~~-3V

-1.SV -OV ---~.I~--~---3V

TIMING INPUT - 1.SV

---'·I'--~---oV ASYNCHRONOUS ----~I,--~~---3V CONTROL ~;.--+--+----

-

1.SV PRESET, CLEAR, ETC. - - - - . " r ' " - -.... ~---- OV

PRESET, CLEAR, - 1.SV

SYNCHRONOUS CONTROL q;s-r--;~~~-

3V

CLOCK ENABLE, ETC. ~ - OV

FIGURE 2. SETUP, HOLD, AND RELEASE TIMING

CONTROL INPUT

FIGURE 4. ENABLE AND DISABLE TIMING

3-96

CL = Load capacitance, includes jig and probe capacitance.

RT = Termination resistance, should be equal to loUT of the Pulse Generator. FIGURE 5. PROPAGATION DELAY

December 1996

Features

• Advanced 0.6 micron CMOS Technology

• Compatible with LCXTM Families of Products

• Supports 5V Tolerant Mixed Signal Mode Operation - Input Can Be 3V or 5V

- Output Can Be 3V or Connected to 5V Bus

• Advanced Low Power CMOS Operation

• Excellent Output Drive Capability:

- Balanced Drives (24mA Sink and Source)

• Low Ground Bounce Outputs

• Hysteresis on All Inputs

Ordering Information

TEMP.

RANGE PKG.

PART NUMBER (oC) PACKAGE NO.

CD74LPT541 AM -40 to 85 20 Ld SOIC M20.3-P CD74LPT541 AOM -40 to 85 20 LdOSOP M20.15-P CD74LPT541 CM -40 to 85 20 Ld SOIC M20.3-P CD74LPT541 COM -40 to 85 20 LdOSOP M20.15-P CD74LPT541M -40 to 85 20 Ld SOIC M20.3-P CD74LPT541OM -40 to 85 20 LdOSOP M20.15-P NOTE: OSOP is commonly known as SSOP.

When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel.

Pinout

CD74LPT541

Fast CMOS 3.3V 8-Bit Buffer/Line Driver

Description

The CD74LPTS41 is an a-bit buffer/line driver designed for driving high capacitive memory loads. With its balanced-drive characteristics, this high-speed, low power device pro-vides lower ground bounce, transmission line matching of signals, fewer line reflections and lower EMI and RFI effects.

This makes it ideal for driving on-board buses and transmis-sion lines. This device offers a flow-through organization for ease of board layout.

The CD74LPTS41 can be driven from either 3.3V or S.OV devices allowing this device to be used as a translator in a mixed 3.3/S.0V system.

CD74LPT541 (SOIC, aSOP)

TOP VIEW

DS 7 D6 0.,

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

3-97

File Number

4200.2

Functional Block Diagram

00 'O"EB

TRUTH TABLE (NOTE 1) INPUTS

OEA

L L H NOTE:

1. H = High Voltage Level L

=

Low Voltage Level X= Don't Care Z = High Impedance

OEB

L L H

Pin Descriptions

PIN NAME DESCRIPTION

OEA,OEa Three-State Output Enable Inputs (Active LOW)

Ox

Data Inputs

Ox

Three-State Outputs

GND Ground

Vce Power

Ox L H X

3-98

OUTPUTS

Ox

L H Z

CD74LPT541

Absolute Maximum Ratings Thermal Information

DC Input Voltage ... -O.5V to 7.0V Thermal Resistance (Typical, Note 2) 9JA (oC/W) DC Output Current. ... 120mA SOIC Package. . . 87

Operating Conditions

Operating Temperature Range ... -40°C to 85°C Supply Voltage to Ground Potential

Inputs and Vee Only .. , ... , ... -O.5V to 7.0V Supply Voltage to Ground Potential

asop

Package. . . .. . . 110 Maximum Junction Temperature ... 150°C Maximum Storage Temperature Range ... -65⁰C to 150°C Maximum Lead Temperature (Soldering 1 Os) ... 300°C

(Lead Tips Only) Outputs and 0/0 Only ... " ... -O.5V to 7.0V

CAUTION: Stresses above those listed in "Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated In the operational sections of this specification is not Implied.

NOTE:

2. 9JA is measured with the component mounted on an evaluation PC board in free air.

Dans le document TECHNICAL ASSISTANCE (Page 117-130)