POWER SUPPLY SPECIFICATIONS

Electrical Specifications

Quiescent Power lee Vee = Max VIN=GND 0.1 10

J1A

Supply Current or Vee

Quiescent Power Alee Vee = Max VIN = Vee - 0.6V 2.0 30

J1A

Supply Current TIL (Note 9)

Inputs HiGH

Dynamic Power leeD Vee = Max, Outputs Open VIN=Vee

-

⁵⁰ ⁷⁵

!lAI

Supply Current xOE = xDIR = GND VIN=GND MHz

(Note 10) One Bit Toggling

50% Duty Cycle

Total Power Supply Ie Vee = Max, Outputs Open VIN = Vee - 0.6V 0.5 O.S rnA Current (Note 12) fl = 10MHz, 50% Duty Cycle VIN=GND

xOE = xDIR = GND One Bit Toggling

Vee = Max, Outputs Open VIN = Vee - 0.6V 2.0 3.3 rnA

fl = 2.5MHz, 50% Duty Cycle VIN=GND (Note 11)

xOE = xDIR = GND 16 Bits Toggling

3-18

CD74LPT16245 Switching Specifications Over Operating Range

(Note 13)

(NOTE 14) CD74LPT16245 CD74LPT16245A

TEST (NOTE 15) (NOTE 15)

PARAMETER SYMBOL CONDITIONS MIN MAX MIN MAX UNITS

Propagation Delay tpLH, CL =50pF 1.5 5.2 1.5 4.6 ns

Ato B, BtoA tpHL RL=500Q

Output Enable Time tpZH, 1.5 7.2 1.5 6.2 ns

xOEtoAorB tPZL

Output Disable Time tpHZ, 1.5 7.2 1.5 5.0 ns

(Note 16) tpLZ

xOEtoAorB

Output Enable Time tpZH, 1.5 7.2 1.5 6.2 ns

xDIR toA or B tPZL

Output Disable Time tpHZ, 1.5 7.2 1.5 5.0 ns

xDIR toAorB tpLZ

(Note 16)

Output Skew (Note 17) tSK(O)

-

^0.5 ^0.5 ^ns

NOTES:

3. For conditions shown as Max or Min, use appropriate value specified under Electrical Specifications for the applicable device type.

4. Typical values are at Vcc = 3.3V, 25°C ambient and maximum loading.

5. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.

6. This parameter is guaranteed but not tested.

7. VOH

=

Vcc - 0.6V at rated current.

8. This parameter is determined by device characterization but is not production tested.

9. Per TIL driven input; all other inputs at VCC or GND.

10. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.

11. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.

12. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = IcC + ~ICC DHNT + ICCD (fcp/2 + flNI) Icc = Quiescent Current (ICCL,ICCH and ICCZ)

~ICC = Power Supply Current for a TIL High Input DH = Duty Cycle for TIL Inputs High

NT = Number of TIL Inputs at DH

ICCD

=

Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCp

=

Clock Frequency for Register Devices (Zero for Non-Register Devices) Ncp = Number of Clock Inputs at fcp

=

Input Frequency NI

=

Number of Inputs at fl

All currents are in milliamps and all frequencies are in megahertz.

13. Propagation Delays and Enable/Disable times are with VCC

=

3.3V ±O.3V, normal range. For VCC

=

2.7V, extended range, all Propaga-tion Delays and Enable/Disable times should be degraded by 20%.

14. See test circuit and wave forms.

15. Minimum limits are guaranteed but not tested on Propagation Delays.

16. This parameter is guaranteed but not production tested.

17. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.

3·19

Test Circuits and Waveforms

NOTE:

18. Pulse Generator for All Pulses: Rate S 1.0MHz; louT s

son;

tf. tr S 2.5ns.

FIGURE 1. TEST CIRCUIT

CONTROL INPUT

OUTPUT NORMALLY LOW

OUTPUT NORMALLY HIGH

FIGURE 2. ENABLE AND DISABLE TIMING

3-20

SWITCH POSITION

TEST SWITCH

tpLZ. tPZL. Open Drain 6V

tpHZ. tPZH GND

tpLH. tpHL Open

DEFINITIONS:

CL = Load capacitance. includes jig and probe capacitance.

=

Termination resistance. should be equal to loUT of the Pulse Generator.

SAME PHASE INPUT TRANsmON

OUTPUT

OPPOSITE PHASE INPUT TRANSmON

, . . - -.... ~~---3V

~---1.5V

' - - - O V

,....-ot~rr--VOH -1.5V _ _ ~_VOL

, . . + - - 3 V -#----1.5V

---"~---OV

FIGURE 3. PROPAGATION DELAY

HARRIS

SEMICONDUCTOR

CD74LPT16373

December 1996

Fast CMOS 3.3V 16-Bit Transparent Latch

Features

• Advanced 0.6 micron CMOS Technology

• Compatible with LCXTM Families of Products

• Supports SV Tolerant Mixed Signal Mode Operation - Input Can Be 3V or SV

- Output Can Be 3V or Connected to SV Bus

• Advanced Low Power CMOS Operation

• Excellent Output Drive Capability:

- Balanced Drives (24mA Sink and Source)

• Pin Compatible with Industry Standard Double-Density Pinouts

• Low Ground Bounce Outputs

• Hysteresis on All Inputs

• Multiple Center Pin and Distributed VcclGND Pins Minimizing Switching Noise

Ordering Information

TEMP.

RANGE PKG.

PART NUMBER

fc)

PACKAGE NO.

CD74LPT16373AMT -40 to 85 48 LdTSSOP M48.240-P CD74LPT16373ASM -40 to 85 48 Ld SSOP M48.300-P CD74LPT16373MT -40 to 85 48 LdTSSOP M48.240-P CD74LPT16373SM -40 to 85 48 LdSSOP M48.300-P NOTE: When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel.

Description

The CD74LPT16373 is a 16-bit transparent latch designed with three-state outputs and is intended for bus oriented applications. The Output Enable and Latch Enable controls are organized to operate as two 8-bit latches or one 16-bit latch. When Latch Enable (LE) is HIGH, the flip-flops appear transparent to the data. The data that meets the set-up time when LE is LOW is latched. When OE is HIGH, the bus out-put is in the high impedance state.

The CD74LPT16373 can be driven from either 3.3V or 5.0V devices allowing this device to be used as a translator in a mixed 3.3/5.0V system.

Pinout

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. File Number

4206.2

©

Harris Corporation 1996

3-21

a.

..J

>

c.)

Functional Block Diagram

TRUTH TABLE (NOTE 1) INPUTS

PIN NAME DESCRIPTION

~ Output Enable Inputs (Active LOW) xLE Latch Enable Inputs (Active HIGH) xDx Data Inputs

><Ox

Three·State Outputs

GND Ground

CD 74LPT16373

Absolute Maximum Ratings

Thermal Information

DC Input Voltage ... -0.5V to 7.0V Thermal Resistance (Typical, Note 2) 9JA (oC/w) DC Output Current ... 120mA TSSOP Package. . . 94 Operating Conditions

Operating Temperature Range ... -40°C to 85°C Supply Voltage to Ground Potential

Inputs and Vee Only ... -0.5V to 7.0V Supply Voltage to Ground Potential

SSOP Package . . . 76 Maximum Junction Temperature ... 150°C Maximum Storage Temperature Range ... -65⁰C to 150°C Maximum Lead Temperature (Soldering 1 Os) ... 300°C

(Lead Tips Only) Outputs and 0/0 Only ... -0.5V to 7.0V

CAUTION: Stresses above those listed in "Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

2. 9JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

(NOTE 3) (NOTE 4)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

DC ELECTRICAL SPECIFICATIONS Over the Operating Range, TA = -40°C to 85°C, Vee = 2.7V to 3.6V

Input HIGH Voltage VIH Guaranteed Logic HIGH Level 2.2 5.5 V

(Input Pins)

Input HIGH Voltage VIH Guaranteed Logic HIGH Level 2.0 5.5 V

(I/O Pins)

Input LOW Voltage VIL Guaranteed Logic LOW Level -0.5 0.8 V

(Input and I/O Pins)

Input HIGH Current IIH Vee = Max VIN=5.5V

-

^±1 ~

(Input Pins)

Input HIGH Current IIH Vee = Max VIN=Vee

-

^±1 ~

(I/O Pins)

Input LOW Current IlL Vee = Max VIN=GND ±1 ~

(Input Pins)

Input LOW Current IlL Vee = Max VIN=GND

-

^±1 ~

(I/O Pins)

High Impedance IOZH Vee = Max VOUT= 5.5V ±1 ~

Output Current

(Three-State) IOZL Vee = Max VOUT=GND

-

^±1 ~

Clamp Diode Voltage VIK Vee = Min, lIN = -18mA -0.7 -1.2 V

Output HIGH Current IOOH Vee = 3.3V, VIN = VIH or VIL, Vo = 1.5V (Note 5) -36 -60 -110 mA Output LOW Current IOOL Vee = 3.3V. VIN = VIH or VIL, Vo = 1.5V (Note 5) 50 90 200 mA

Output HIGH Voltage VOH Vee = Min, VIN = VIH or VIL IOH=-0.1mA Vee- 0.2 V

IOH=-3mA 2.4 3.0

-

Vee = 3.0V, VIN = VIH or VIL IOH=-8mA 2.4 3.0 V

(Note 7)

IOH=-24mA 2.0

-

Output LOW Voltage VOL Vee = Min, VIN = VIH or VIL IOL=0.1mA

-

^0.2 ^V

IOL = 16mA

-

^0.2 ^0.4 ^V

IOL=24mA

-

^0.3 ^0.5 ^V

3-23

Electrical Specifications

(Continued)

(NOTE 3) (NOTE 4)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Short Circuit Current loS Vee = Max (Note 5), VOUT = GND ·60 ·85 ·240 mA

(Note 6)

Power Down Disable 10FF Vee = OV, VIN orVOUTS4.5V ±100

J1A

Input Hysteresis VH 150 mV

CAPACITANCE TA = 25°C, 1 =1MHz

Input Capacitance CIN VIN=OV 4.5 6 pF

(Note 8)

Output Capacitance CoUT VOUT=OV 5.5 8 pF

(Note 8)

POWER SUPPLY SPECIFICATIONS

Quiescent Power Icc Vee~Max VIN=GNb 0.1 10

J1A

Supply Current or Vee

Quiescent Power ~Iee Vee = Max VIN = VCC • 0.6V

-

^2.0 ³⁰

J1A

Supply Current TTL (Note 9)

Inputs HIGH

Dynamic Power IceD Vee = Max, Outputs Open VIN=Vee 50 75

JJ.AI

Supply Current x<:>E=GND VIN=GND MHz

(Note 10) xLE=Vee

One Bit Toggling 50% Duty Cycle

Total Power Supply Ie Vee

=

Max, Outputs Open VIN = Vee· 0.6V 0.6 2.3 mA Current (Note 12) 11 = 10MHz, 50% Duty Cycle VIN=GND

xOE=GND xLE=Vee One BitToggling

Vee

=

Max, Outputs Open VIN

=

Vee· 0.6V 2.1 4.7 mA

11 = 2.5MHz, 50% Duty Cycle VIN=GND (Note 11)

xOE=GND xLE=Vee 16 Bits Toggling

3·24

CD74LPT16373

Switching Specifications Over Operating Range (Note 13)

CD74LPT16373 CD74LPT16373A (NOTE 14)

TEST (NOTE 15) (NOTE 15)

PARAMETER SYMBOL CONDITIONS MIN MAX MIN MAX UNITS

Propagation Delay tpLH, CL = 50 pF 1.5 7.0 1.5 5.2 ns

xDxto xOx tpHL RL=500n

Propagation Delay tPLH, 2.0 7.0 2.0 6.5 ns

x LEto xOx tpHL

Output Enable Time tpZH, 1.5 7.2 1.5 6.5 ns

XOE to xOx tPZL

Output Disable Time tpHZ, 1.5 7.2 1.5 5.5 ns

(Note 16) tpLZ

xOEtoxOx

Setup Time HIGH tsu 2.0 2.0

-

^ns

or LOW, xDx to xLE

Hold lime HIGH tH 1.5 1.5 ns

or LOW, XDX to XLE

xLE Pulse Width tw 6.0 5.0

-

^ns

HIGH (Note 16)

Output Skew tSK(O) 0.5 0.5 ns

(Note 17) NOTES:

3. For conditions shown as Max or Min, use appropriate value specified under Electrical Specifications for the applicable device type.

4. Typical values are at VCC = 3.3V, 25°C ambient and maximum loading.

5. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.

6. This parameter is guaranteed but not tested.

7. VOH = VCC - 0.6V at rated current.

8. This parameter is determined by device characterization but is not production tested.

9. Per TTL driven input; all other inputs at V CC or GND.

10. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.

11. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.

12. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = Icc + AICC DHNT + ICCD (fcP/2 + flNI) Icc = Quiescent Current

AICC = Power Supply Current for a TTL High Input DH = Duty Cycle for TTL Inputs High

NT = Number of TTL Inputs at DH

ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCp = Clock Frequency for Register Devices (Zero for Non-Register Devices) fl = Input Frequency

NI = Number of Inputs at fl

All currents are in milliamps and all frequencies are in megahertz.

13. Propagation Delays and Enable/Disable times are with Vcc = 3.3V ±O.3V, normal range. For VCC = 2.7V, extended range, all Propaga-tion Delays and Enable/Disable times should be degraded by 20%.

14. See test circuit and wave forms.

15. Minimum limits are guaranteed but not tested on Propagation Delays.

16. This parameter is guaranteed but not production tested.

17. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.

3-25

Test Circuits and Waveforms

18. Pulse Generator for All Pulses: Rate:s; 1.0MHz; ZOUT :s;

son;

tf, tr :s; 2.5ns.

FIGURE 1. TEST CIRCUIT

- ~~~S88-3V

-1.SV

SYNCHRONOUS CONTROL q;.s--I.~~~~-3V

CLOCK ENABLE, ETC. ~ - OV

FIGURE 2. SETUP, HOLD, AND RELEASE TIMING

CONTROL INPUT

OUTPUT NORMALLY LOW

OUTPUT NORMALLY HIGH

FIGURE 4. ENABLE AND DISABLE TIMING

3-26

CL = Load capacitance, includes jig and probe capacitance.

=

Termination resistance, should be equal to ZoUT of the Pulse Generator. FIGURE 5. PROPAGATION DELAY

Dans le document TECHNICAL ASSISTANCE (Page 49-57)