Absolute Maximum Ratings Thermal Information

DC Input Voltage ...

-o.sv

to 7.0V Thermal Resistance (Typical, Note 2) 9JA (oCIW) DC Output Current ... 120mA SOIC Package. . . 87

asop

Package. . . 110

Operating Conditions

Maximum Junction Temperature ... 1S0oC Operating Temperature Range ... -40°C to 85°C Maximum Storage Temperature Range ... -65⁰C to 150°C Supply Voltage to Ground Potential Maximum Lead Temperature (Soldering 10s) ... 300°C

Inputs and Vee Only ... -0.5V to 7.0V (Lead Tips Only) Supply Voltage to Ground Potential

Outputs and 0/0 Only ... -0.5V to 7.0V

CAUTION: Stresses above those listed In "Absolute Maximum Ratings" may cause permanent damage to the device. This Is a stress only rating and operation of the device at these or any other conditions above those Indicated in the operational sections of this specification Is not Implied.

NOTE:

2. 9JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

(NOTE 3) (NOTE 4)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

DC ELECTRICAL SPECIFICATIONS Over the Operating Range, TA = -40⁰C to 8SoC, Vee = 2.7V to 3.6V

Input HIGH Voltage VIH Guaranteed LogiC HIGH Level 2.2 S.S V

(Input Pins)

Input HIGH Voltage VIH Guaranteed Logic HIGH Level 2.0 5.5 V

(I/O Pins)

Input LOW Voltage VIL Guaranteed Logic LOW Level -0.5 0.8 V

(Input and I/O Pins)

Input HIGH Current IIH Vee = Max VIN =5.SV ±1

I1A

(Input Pins)

Input HIGH Current IIH Vee = Max VIN = Vee ±1

I1A

(I/O Pins)

Input LOW Current IlL Vee = Max VIN=GND ±1

I1A

(Input Pins)

Input LOW Current IlL Vee = Max VIN=GND ±1

I1A

(I/O Pins)

High Impedance IOZH Vee = Max VOUT=S.5V

-

^±1

I1A

Output Current

(Three-State) IOZL Vee = Max VOUT=GND ±1

I1A

Clamp Diode Voltage VIK Vee

=

Min, liN = -1BmA -0.7 -1.2 V

Output HIGH Current IOOH Vee = 3.3V, VIN = VIH or VIL, Vo = 1.SV (Note 5) -36 -60 -110 mA Output LOW Current IOOL Vee = 3.3V, VIN = VIH orVIL, Vo= 1.SV (Note 5) SO 90 200 mA Output HIGH Voltage VOH Vee = Min, VIN = VIH or Vil IOH=-0.1mA Vee - 0.2

-

IOH=-3mA 2.4 3.0 V

Vee = 3.0V, VIN = VIH or Vil IOH=-8mA 2.4 3.0 V

(Note 7)

IOH =-24mA 2.0

-

Output LOW Voltage VOL Vee = Min, VIN = VIH or Vil IOl = 0.1mA

-

^0.2 ^V

IOl = 16mA 0.2 0.4 V

IOL=24mA 0.3 0.5 V

3-111

Electrical Specifications (Continued)

(NOTE 3) (NOTE 4)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Short Circuit Current lOS Vce = Max (Note 5), VOUT = GND -60 -85 -240 mA

(Note 6)

Power Down Disable IOFF Vee = OV, VIN or VOUT ~ 4.5V ±100 ~A

Input Hysteresis VH 150 mV

CAPACITANCE TA = 25°C, f = 1 MHz

Input Capacitance CIN VIN =OV 4.5 6 pF

(Note 8)

Output Capacitance COUT VOUT=OV

-

^5.5 ⁸ ^pF

(Note 8)

POWER SUPPLY SPECIFICATIONS

Quiescent Power Icc Vee = Max VIN=GND 0.1 10 ~

Supply Current or Vee

Quiescent Power alec Vee = Max VIN = VCC - 0.6V 2.0 30 ~

Supply Current TTL (Note 9)

Inputs HIGH

Dynamic Power IceD Vee = Max, Outputs Open VIN = Vee 50 75 ~

Supply Current OE=GND VIN=GND MHz

(Note 10) One Bit Toggling

50% Duty Cycle

Total Power Supply Ie Vee = Max, Outputs Open VIN = Vee - 0.6V 0.6 2.3 mA

Current (Note 12) fl = 10MHz, 50% Duty Cycle VIN=GND OE=GND

One BitToggling

Vee = Max, Outputs Open VIN = Vee - 0.6V

-

^2.1 ^4.7 ^mA

fl = 2.5MHz, 50% Duty Cycle VIN=GND (Note 11)

OE=GND 8 Bits Toggling

3-112

CD74LPT573 Switching Specifications Over Operating Range

(Note 13)

(NOTE 14) CD74LPT573 CD74LPT573A CD74LPT573C

TEST (NOTE 15) (NOTE 15) (NOTE 15)

PARAMETER SYMBOL CONDITIONS MIN MAX MIN MAX MIN MAX UNITS

Propagation Delay tpLH, CL = 50pF 1.5 8.0 1.5 5.2 1.5 4.2 ns

DX to

Ox

tpHL RL=

soon

Propagation Delay tpLH, 2.0 12.0 2.0 8.5 2.0 5.5 ns

LE to

Ox

tpHL

Output Enable Time tpZH, 1.5 9.5 1.5 6.5 1.5 5.5 ns

OE to

Ox

tPZL

Output Disable Time tpHZ, 1.5 6.5 1.5 5.5 1.5 5.0 ns

(Note 16) tpLZ

OE to

Ox

Setup Time HIGH or tsu 2.0 2.0 2.0

-

^ns

LOW, DxtoLE

Hold Time HIGH or tH 1.5 1.5 1.5 ns

LOW, DxtoLE

LE Pulse Width HIGH tw 6.0 5.0 5.0 ns

(Note 16)

Output Skew (Note 17) tSK(O) 0.5 0.5 0.5 ns

NOTES:

3. For conditions shown as Max or Min, use appropriate value specified under Electrical Specifications for the applicable device type.

4. Typical values are at Vcc = 3.3V, 25°C ambient and maximum loading.

5. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.

6. This parameter is guaranteed but not tested.

7. VOH = Vcc - 0.6V at rated current.

8. This parameter is determined by device characterization but is not production tested.

9. Per TTL driven input; all other inputs at Vcc or GND.

10. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.

11. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.

12. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + dlcc DHNT + ICCD (fcp/2 + flNI) ICC

=

Quiescent Current

dlCC

=

Power Supply Current for a TTL High Input DH

=

Duty Cycle for TTL Inputs High

=

Number of TTL Inputs at DH

ICCD

=

Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCp = Clock Frequency for Register Devices (Zero for Non-Register Devices) fl = Input Frequency

=

Number of Inputs at fl

All currents are in milliamps and all frequencies are in megahertz.

13. Propagation Delays and Enable/Disable times are with Vcc

=

3.3V ±O.3V, normal range. For Vcc

=

2.7V, extended range, all Propaga-tion Delays and Enable/Disable times should be degraded by 20%.

14. See test circuit and wave forms.

15. Minimum limits are guaranteed but not tested on Propagation Delays.

16. This parameter is guaranteed but not production tested.

17. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.

3-113

Test Circuits and Waveforms

FIGURE 1. TEST CIRCUIT

-:~88~~-3V

_-1.5V

SYNCHRONOUS CONTROL ~;§-r--;~~~-3V

PRESET, CLEAR, - - 1.5V

CLOCK ENABLE, ETC. ~ - OV

FIGURE 2. SETUP, HOLD, AND RELEASE TIMING

CONTROL INPUT

FIGURE 4. ENABLE AND DISABLE TIMING

SWITCH POSITION

=

Load capacitance, includes jig and probe capacitance.

RT = Termination resistance, should be equal to ZOUT of the Pulse Generator. FIGURE 5. PROPAGATION DELAY

3-114

CD74LPT646, CD74LPT652

December 1996

Fast CMOS 3.3V 8-Bit Registered Transceivers

Features

• Advanced 0.6 micron CMOS Technology

• Compatible with LCXTM Families of Products

• Supports

SV

Tolerant Mixed Signal Mode Operation - Input Can Be

3V

SV

- Output Can Be

3V

or Connected to

SV

Bus

• Advanced Low Power CMOS Operation

• Excellent Output Drive Capability:

- Balanced Drives (24mA Sink and Source)

• Low Ground Bounce Outputs

• Hysteresis on All Inputs

Pinout

bus transceiver with three-state Ootype flip-flops and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage regis-ters. The C074LPT652 utilizes GAB and GBA signals to control the transceiver functions. The C074LPT646 utilizes the enable control (G) and direction pins (OIR) to control the transceiver functions. SAB and SBA control pins are used to select either real-time or stored data transfer. The circuitry used for select control will eliminate the typical decoding glitch that occurs in a multiplexer during the transition between real-time and stored data. A low input level selects real-time data and a high selects stored data.

The C074LPT646 and C074LPT652 can be driven from

CD74LPT6460M -40 to 85 24LdOSOP M24.15-P CD74LPT646AOM -40 to 85 24 LdOSOP M24.15-P CD74LPT646COM -40 to 85 24 LdOSOP M24.15-P CD74LPT646M -40 to 85 24 Ld SOIC M24.3-P CD74LPT646AM -40 to 85 24Ld SOIC M24.3-P CD74LPT646CM -40 to 85 24 LdSOIC M24.3-P CD74LPT6520M -40 to 85 24 LdOSOP M24.15-P CD74LPT652AOM -40 to 85 24 LdOSOP M24.15-P CD74LPT652COM -40 to 85 24 LdOSOP M24.15-P CD74LPT652M -40 to 85 24 LdSOIC M24.3-P CD74LPT652AM -40 to 85 24 Ld SOIC M24.3-P CD74LPT652CM -40 to 85 24 LdSOIC M24.3-P NOTE:

asap

is commonly known as SSO?

When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. File Number

4257

3-115

Functional Block Diagram

FUNCTION/OPERATION

G

Isolation H

FUNCTION/OPERATION GAB

GSA

Isolation L H

Store A and B Data L H

Store A, Hold B X H

Store A in Both Registers H H

TO 7 OTHER CHANNELS

...

TRUTH TABLE (CD74LPT646) INPUTS

TRUTH TABLE (CD74LPT652)

INPUTS

Input Unspecified Input Output

(Note 1)

CD74LPT646, CD74LPT652

TRUTH TABLE (CD74LPT652) (Continued)

(NOTES 1, 2)

INPUTS DATAUO

FUNCTION/OPERATION GAB GBA CPAB CPBA SAB SBA

Ao-

A7 Bo-B7

Hold A, Store B L X HorL

i

X X Unspecified Input

Store B in Both Registers L L

i i

X X (Note 2) Output Input

(Note 1)

Real Time B Data to A Bus L L X X X L Output Input

Stored B Data to A Bus L L X HorL X H

Real Time A Data to B Bus H H X X L X Input Output

Stored A Data to B Bus H H H orL X H X

Stored A Data to B Bus H L H orL H orL H H Output Output

and Stored B Data toA Bus NOTES:

1. The data output functions may be enabled or disabled by various signals at the

G

or DIR for the CD74LPT646 type and GAB or GBA for CD74LPT652 type inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH tran-sition on the clock inputs.

2. Select Control

=

L: clocks can occur simultaneously.

Select Control

=

H: clocks must be staggered in order to load both registers.

=

High Voltage Level L

=

Low Voltage Level X= Don't Care

i =

LOW-to-HIGH transition

3-117

-v--CD74LPT646 DIR CPAB CPBA SAB SBA CD74LPT646 DIR

tI

CPAB CPBA SAB SBA

L L X X X L H L X X L X

CD74LPT652 GAB

tIIA

CPAB CPBA SAB SBA CD74LPT652 GAB

tIIA

CPAB CPBA SAB SBA

L L X X X L H H X X L X

FIGURE 1. REAL-TIME TRANSFER BUS B TO A FIGURE 2. REAL-TIME TRANSFER BUS A TO B

-v--CD74LPT646 DIR

tI

CPAB CPBA SAB SBA

(NOTE 3) L L X HorL X H

CD74LPT646 DIR CPAB CPBA SAB SBA

H L

t

X X X

L L X

t

^X ^X

X H

t t

^X ^X ^H ^L ^HorL ^X ^H ^X

CD74LPT652 GAB

tIIA

CPAB CPBA SAB SBA H L HorL HorL H H CD74LPT652 GAB

tIIA

CPAB CPBA SAB SBA

X H

t

^X ^X ^X

L X X

t

^X ^X

L H

t

^X ^X

FIGURE 3. STORAGE FROM A AND/OR B FIGURE 4. TRANSFER STORES DATA TO A AND/OR B NOTE:

3. Cannot transfer data to A bus and B bus simultaneously.

Pin Descriptions

PIN NAME DESCRIPTION

Ao-

^A⁷ Data Register A Inputs, Data Register B Outputs

Bo-B7 Data Register B Inputs, Data Register A Outputs

CPAB,CPBA Clock Pulse Inputs

SAB, SBA Output Data Source Select Inputs

DIR,G Output Enable Inputs (CD74LPT646)

GAB,GBA Output Enable Inputs (CD74LPT652)

GND Ground

Vee

^Power

3-118

CD74LPT646, CD74LPT652

Absolute Maximum Ratings Thermal Information

DC Input Voltage ... -0.5V to 7.0V Thermal Resistance (Typical, Note 4) 9JA (oCIW) DC Output Current. ... 120mA SOIC Package. . . 75

Operating Conditions

Operating Temperature Range ... -40°C to 8SoC

asop

Package. . . 100 Maximum Junction Temperature ... 150°C Maximum Storage Temperature Range ... -65⁰C to 150°C Supply Voltage to Ground Potential

Inputs and Vee Only ... , ... ,. -0.5V to 7.0V Supply Voltage to Ground Potential

Maximum Lead Temperature (Soldering 1 Os) ... 300°C (Lead Tips Only)

Outputs and DIO Only ... -O.SV to 7.0V

CAUTION: Stresses above those listed In "Absolute Maximum Ratings' may cause permanent damage to the device. This Is a stress only rating and operation of the device at these or any other conditions above those Indicated In the operatlonsl sections of this specification Is not Implied.

NOTE:

4. 9JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

(NOTES) (NOTE 6)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

DC ELECTRICAL SPECIFICATIONS Over the Operating Range, TA = -40°C to 85°C, Vee = 2.7V to 3.6V

Input HIGH Voltage VIH Guaranteed LogiC HIGH Level 2.2 5.5 V

Electrical Specifications

(Continued)

(NOTE 5) (NOTE 6)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

CAPACITANCE TA = 25°C, f= 1MHz

Input Capacitance CIN VIN=OV 4.5 6 pF

(Note 10)

Output Capacitance COUT VOUT=OV 5.5 8 pF

(Note 10)

POWER SUPPLY SPECIFICATIONS

Quiescent Power lee Vee = Max VIN=GND 0.1 10

J1A

Supply Current or Vee

Quiescent Power _~Iee Vee = Max VIN = Vee· 0.6V 2.0 30

J1A

Supply Current TIL (Note 11)

Inputs HIGH

Dynamic Power leeD Vee = Max, Outputs Open VIN = Vee 50 75

JlAI

Supply G=DIR=GND VIN=GND MHz

(Note 12) One Bit Toggling

50% Duty Cycle

Total Power Supply Ie Vee = Max, Outputs Open VIN = Vee· 0.6V

.

_0.6 2.3' mA Current (Note 14) fl = 10MHz, 50% Duty Cycle VIN=GND

G

= DIR = GND or GAB =

GSA

= GND One Bit Toggling

Vee = Max, Outputs Open VIN = Vee· 0.6V 2.1 4.7 mA

fl = 2.5MHz, 50% Duty Cycle VIN=GND (Note 13)

G

= DIR = GND or GAB =

GSA

= GND 8 Bits Toggling

Dans le document TECHNICAL ASSISTANCE (Page 142-151)