Operating Conditions - TECHNICAL ASSISTANCE

Operating Temperature Range ... -40°C to 85°C Supply Voltage to Ground Potential

Inputs and Vee Only ... -0.5V to 7.0V Supply Voltage to Ground Potential

SSOP Package . . . 76 Maximum Junction Temperature ... 150°C Maximum Storage Temperature Range ... -65⁰C to 150°C Maximum Lead Temperature (Soldering lOs) ... 300°C

(Lead Tips Only) Outputs and 0/0 Only ... -0.5V to 7.0V

CAUTION: Stresses above those I/st9d in -Absolute Maximum Ratings- may cause permanent damage to the device. This is a stress only rating and operation of the d9vice at these or any other conditions above those Indicat9d In the operational sections of this specification is not impll9d.

NOTE:

2. 9JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

(NOTE 3) (NOTE 4)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

DC ELECTRICAL SPECIFICATIONS Over the Operating Range, TA = -40°C to 85°C, Vee = 2.7V to 3.6V

Input HIGH Voltage VIH Guaranteed Logic HIGH Level 2.2 5.5 V

(Input Pins)

Input HIGH Voltage VIH Guaranteed Logic HIGH Level 2.0 5.5 V

(1/0 Pins)

Input LOW Voltage VIL Guaranteed Logic LOW Level -0.5 0.8 V

(Input and 1/0 Pins)

Input HIGH Current IIH Vee = Max VIN= 5.5V

-

^±1 ^~

(Input Pins)

Input HIGH Current IIH Vee = Max VIN=Vee

-

^±1 ~

(1/0 Pins)

Input LOW Current IlL Vee = Max VIN=GND

-

^±1 ^~

(Input Pins)

Input LOW Current IlL Vee = Max VIN=GND ±1 ~

(1/0 Pins)

High Impedance IOZH Vee = Max Vour=5.5V

-

^±1 ^~

Output Current

(Three-State Output IOZL Vee = Max Vour=GND ±1 ~

Pins)

Clamp Diode Voltage VIK Vee = Min, liN = -18mA

-

^-0.7 ^-1.2 ^V

Output HIGH Current IODH Vee = 3.3V, VIN = VIH or VIL, Vo = 1.5V (Note 5) -36 -60 -110 mA Output LOW Current IODL Vee = 3.3V, VIN = VIH or VIL, Vo = 1.5V (Note 5) 50 90 200 mA

Output HIGH Voltage VOH Vee = Min, VIN = VIH or VIL IOH =-O.lmA Vee- 0.2 V

IOH=-3mA 2.4 3.0 V

Vee = 3.0V, VIN = VIH orVIL IOH=-8mA 2.4 3.0 V

(Note 7)

IOH=-24mA 2.0 V

Output LOW Voltage VOL Vee = Min, VIN = VIH or VIL IOL = O.lmA 0.2 V

IOL= 16mA 0.2 0.4 V

IOL=24mA 0.3 0.5 V

3-29

Electrical Specifications

(Continued)

(NOTE 3) (NOTE 4)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Short Circuit Current lOS Vee = Max (Note 5), VOUT = GND ·60 ·85 ·240 mA

(Note 6)

Power Down Disable 10FF Vee = OV, VIN or VOUT ~.5V

·

^±100

ItA

Input Hysteresis VH

·

¹⁵⁰ ^mV

CAPACITANCE TA = 25°C, f = 1 MHz

Input Capacitance CIN VIN=OV 4.5 6 pF

(Note B)

Output Capacitance COUT VOUT=OV

·

^5.5 ⁸ ^pF

(Note B)

POWER SUPPLY SPECIFICATIONS

Quiescent Power lee Vee = Max VIN=GND

·

^0.1 ¹⁰

ItA

Supply Current or Vee

Quiescent Power alce Vce=Max VIN = Vec· 0.6V 2.0 30

ItA

Supply Current TTL (Note 9)

Inputs HIGH

Dynamic Power leeD Vee = Max, Outputs Open VIN= Vcc

·

⁵⁰ ⁷⁵

JlAI

Supply Current xOE=GND VIN=GND MHz

(Note 10) One BitToggling

50% Duty Cycle

Total Power Supply Ie Vee = Max, Outputs Open VIN = Vee· 0.6V

·

^0.6 ^2.3 ^mA

Current (Note 12) 'I = 10MHz, 50% Duty Cycle VIN=GND xOE=GND

One Bit Toggling

Vee = Max, Outputs Open VIN = Vee· 0.6V

·

^2.1 ^4.7 ^mA

fl = 2.5MHz, 50% Duty Cycle VIN=GND (Note 11)

xOE=GND 16 Bits Toggling

3-30

CD74LPT16374 Switching Specifications Over Operating Range

(Note 13)

CD74LPT16374 CD74LPT16374A

(NOTE 14)

TEST (NOTE 15) (NOTE 15)

PARAMETER SYMBOL CONDITIONS MIN MAX MIN MAX UNITS

Propagation Delay tPLH, CL = 50pF 2.0 7.0 2.0 6.5 ns

XCLKXto xOx tpHL RL =5000

Output Enable Time tpZH, 1.5 7.2 1.5 6.5 ns

xOEtoxOx tPZL

Output Disable Time tpHZ, 1.5 7.2 1.5 5.5 ns

(Note 16) tpLZ

xOEto

xOx

Setup TIme HIGH or tsu 2.0 2.0 ns

LOW, xDX to xCLK

Hold Time HIGH or LOW, tH 1.5

-

^1.5 ^ns

xDxtoxCLK

xCLK Pulse Width HIGH tw 7.0 5.0 ns

or LOW (Note 16)

Output Skew tSK(O) 0.5

-

^0.5 ^ns

(Note17) NOTES:

3. For conditions shown as Max or Min, use appropriate value specified under Electrical Specifications for the applicable device type.

4. Typical vaiues arEi at Vcc = 3.3V, 25°C ambient and maximum loading.

5. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.

6. This paramEiter Is guaranteed but not tested.

7. VOH = VCC - 0.6Vat rated current.

8. This parameter is determined by device characterization but is not production tested.

9. Per TTL driven Input; all other Inputs at VCC or GND.

10. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.

11. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.

12. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC == ICC + AICC DHNT + ICCD (fcpl2 + flNI) lex:

=

Quiescent Current

Alcc = Power Supply Current for a TTL High Input DH == Duty Cycle for TTL Inputs High

NT = Number of TTL Inputs at DH

Iceo = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCp

=

Clock Frequency for Register Devices (Zero for Non-Register DeviCEis) NCp = Number of Clock Inputs at fcp

=

Input Frequency NI = Number of Inputs at fl

All currents are in milliamps and all frequencies are in megahertz.

13. Propagation Delays and Enable/Disable times are with Vcc = 3.3V ±O.3V, normal range. For VCC = 2.7V, extended range, all Propaga-tion Delays and Enable/Disable times should be degraded by 20%.

14. See test circuit and wave forms.

15. Minimum limits are guaranteed but not tested on Propagation Delays.

16. This parameter is guaranteed but not production tested.

17. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.

3-31

Test Circuits and Waveforms

NOTE:

18. Pulse Generator for All Pulses: Rate:5: 1.0MHz; ZOUT :5:

son;

tf. tr :5: 2.5ns.

FIGURE 1. TEST CIRCUIT

-:~~~~-3V

'-1.5V

SYNCHRONOUS CONTROL ~;""1.~~~~8-

3V

CLOCK ENABLE, ETC. ~ - OV

FIGURE 2. SETUP, HOLD, AND RELEASE TIMING

CONTROL INPUT

FIGURE 4. ENABLE AND DISABLE TIMING

3-32

=

Load capacitance. includes jig and probe capacitance.

RT = Termination reSistance. should be equal to ZOUT of the Pulse Generator. FIGURE 5. PROPAGATION DELAY

HARRIS

SEMICONDUCTOR

CD74LPT16501

December 1996

Fast CMOS 18-Bit Registered Transceiver

Features

• Advanced 0.6 micron CMOS Technology

• Compatible with LCXTM Families of Products

• Supports 5V Tolerant Mixed Signal Mode Operation - Input Can Be 3V or 5V

- Output Can Be 3V or Connected to 5V Bus

• Advanced Low Power CMOS Operation

• Excellent Output Drive Capability:

- Balanced Drives (24mA Sink and Source)

• Pin Compatible with Industry Standard Double-Density Pinouts

• Low Ground Bounce Outputs

• Hysteresis on All Inputs

• Multiple Center Pin and Distributed VCclGND Pins Minimizing Switching Noise

Ordering Information

TEMP.

RANGE PKG.

PART NUMBER (oC) PACKAGE NO.

CD74LPT16501AMT -40 to 85 56 LdTSSOP M56.240-P CD74LPT16501ASM -40 to 85 56 Ld SSOP M56.300-P CD74LPT16501 MT -40 to 85 56 LdTSSOP M56.240-P CD74LPT16501 SM -40 to 85 56 Ld SSOP M56.300-P NOTE: When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel.

Description

The CD74LPT16S01 is an 18-bit registered bus transceiver designed with D-type latches and flip-flops to allow data flow in transparent, latched, and clocked modes. The Output Enable (OEAB and OEBA), Latch Enable (LEAB and LEBA) and Clock (CLKAB and CLKBA) inputs control the data flow in each direction. When LEAB is HIGH, the device operates in transparent mode for A-to-B data flow. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH or LOW logic level. The A bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CLKAB, if LEAB is LOW. OEAB performs the output enable function on the B port. Data flow from B port to A port is similar using OEBA, LEBA and CLKBA. This high-speed, low power device offers a flow-through organization for ease of board layout.

The CD74LPT16S01 can be driven from either 3.3V or S.OV devices allowing this device to be used as a translator in a mixed 3.3V/S.OV system.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

File Number

4208.1

3-33

....

a.

...I

>

_C")

co;

Pinout

CD74LPT16501 (SSOP, TSSOP) TOP VIEW

56 GND CLI(AB Bo GND B1 B2

Vee

B3 B4 B5 GND

As

A7 B7

A9 B9

A10 B10

A11 B11

GND GND

A12 B12

A13 B13

A14 B14

Vee Vee

A15 B15

A16 B16

GND GND

A17 B17

~ CLKBA

LEBA 29 GND

3-34

CD74LPT16501 Functional Block Diagram

...

TO 17 OTHER CHANNELS

TRUTH TABLE (NOTES 1,4) INPUTS

OEAB LEAS CLKAB Ax

L X X X

H H X L

H H X H

H L

i

H L

i

H L L X

H L H X

NOTES:

1. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, and CLKBA.

2. Output levElI before the indicated steady-state input conditions were established.

3. Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW.

4. H = High Voltage Level L

=

Low Voltage Level Z

=

High Impedance

i

= LOW-to-HIGH Transition

3-35

OUTPUTS Sx

Z L H L H B (Note 2) B (Note 3)

Pin Descriptions

PIN NAME DESCRIPTION

OEAB A-to-B Output Enable Input

OEBA B-to-A Output Enable Input (Active LOW) LEAB A-to-B Latch Enable Input

LEBA B-to-A Latch Enable Input CLKAB A-to-B Clock Input CLKBA B-to-A Clock Input Ax A-to-B Data Inputs or B-to-A

Three-State Outputs Bx B-to-A Data Inputs or A-to-B

Three-State Outputs

GND Ground

Vee

^Power

3-36

CD74LPT16501

Absolute Maximum Ratings Thermal Information

DC Input Voltage ... -0.5V to 7.0V Thermal Resistance (Typical, Note 5) 9JA (oCIW) DC Output Current ... 120mA TSSOP Package. . . 85

Dans le document TECHNICAL ASSISTANCE (Page 60-68)