The CD74LPT827 is a 10-bit wide non-inverting bus driver providing high-performance bus interface buffering for wide address/data paths or buses carrying parity. The 10-bit buff-ers have NAND-ed output enables for maximum control flex-ibility. They are designed for high-capacitance load drive capability, while providing low-capacitance bus loading at both inputs and outputs.
The CD74LPT827 can be driven from either 3.3V or S.OV devices allowing this device to be used as a translator in a mixed 3.3/S.0V system.
Ordering Information
TEMP.
RANGE PKG.
PART NUMBER COC} PACKAGE NO.
CD74LPT827 AQM -40 to 85 24 LdaSOp M24.15-P CD74LPT827BQM -40 to 85 24 Ldasop M24.15-P CD74LPT827CQM -40 to 85 24 Ld asop M24.15-P CD74LPT827 AM -40 to 85 24 Ld SOIC M24.3-P CD74LPT827BM -40 to 85 24 Ld SOIC M24.3-P CD74LPT827CM -40 to 85 24 Ld SOIC M24.3-P NOTE: QSOP is commonly known as SSOP.
When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
File Number
4258
Copyright © Harris Corporation 1996
3-123
Functional Block Diagram
FUNCTION Transparent
Three-State
NOTE:
. 1. H = High Voltage Level L
=
Low Voltage Level X= Don't Care Z=
High ImpedancePin Description
0E
1 L L H XPIN NAME DESCRIPTION
TRUTH TABLE (NOTE 1) INPUTS
0E
2 L L X HDEN
Output Enable Input (Active LOW) Do-09 10-Bit Data InputsYo-Yg 10-Bit Data Outputs
GND Ground
Vee Power
3-124
OUTPUT
DN YN
L L
H H
X Z
X Z
CD 74LPT827
Absolute Maximum Ratings
Thermal Information
DC Input Voltage ... -0.5V to 7.0V Thermal Resistance (Typical, Note 2) 9JA (oCIW) DC Output Current. ... 120mA
asop
Package. . . .. . . 75 Operating ConditionsOperating Temperature Range ... -40°C to 85°C Supply Voltage to Ground Potential
Inputs and Vee Only ... -0.5V to 7.0V Supply Voltage to Ground Potential
SOIC Package. . . 100 Maximum Junction Temperature ... 150°C Maximum Storage Temperature Range ... -65oC to 150°C Maximum Lead Temperature (Soldering 10s) ... 300°C
(Lead Tips Only) Outputs and % Only ... -0.5V to 7.0V
CAUTION: Stresses above those listed In "Absolute Maximum Ratings' may cause permanent damage to the device. This Is a stress only raUng and operaUon of the device at these or any other conditions above those indicated In the operational sections of this speciflcatlon is not Implied.
NOTE:
2. 9JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
(NOTE 3) (NOTE 4)
PARAMETER SYMBOL TEST CONDITIONS MIN TYP
MAX
UNITSDC ELECTRICAL SPECIFICATIONS Over the Operating Range, TA = -40°C to 85°C, Vee = 2.7V to 3.6V
Input HIGH Voltage VIH Guaranteed Logic HIGH Level 2.2
-
5.5 V(Input Pins)
Input HIGH Voltage VIH Guaranteed Logic HIGH Level 2.0 5.5 V
(I/O Pins)
Input LOW Voltage VIL Guaranteed Logic LOW Level -0.5 0.8 V
(Input and I/O Pins)
Input HIGH Current IIH Vee = Max VIN= 5.5V
-
±5J1A
(Input Pins)
Input HIGH Current IIH Vee = Max VIN=Vee
-
±5J1A
(I/O Pins)
Input LOW Current IlL Vee = Max VIN=GND ±5
J1A
(Input Pins)
Input LOW Current IlL Vee = Max VIN=GND
-
±5J1A
(I/O Pins)
High Impedance IOZH Vee = Max Vour= 5.5V
-
±5J1A
Output Current
(Three-State Output IOZL Vee = Max Vour=GND ±5
J1A
Pins)
Clamp Diode Voltage VIK Vee = Min, liN = -18mA -0.7 -1.2 V
Output HIGH Current IOOH Vee = 3.3V, VIN = VIH or VIL, Vo = 1.5V (Note 5) -36 -60 -110 mA Output LOW Current IOOL Vee = 3.3V, VIN = VIH or VIL, Vo = 1.5V (Note 5) 50 90 200 mA
Output HIGH Voltage VOH Vce = Min, VIN = VIH orVIL IOH = -0.1mA Vce- 0.2 V
IOH=-3mA 2.4 3.0 V
Vee = 3.0V, VIN = VIH or VIL IOH=-8mA 2.4 3.0
-
V(Note 7)
IOH=-24mA 2.0 V
Output LOW Voltage VOL Vee = Min, VIN = VIH or VIL IOL = 0.1mA 0.2 V
IOL = 16mA 0.2 0.4 V
IOL=24mA 0.3 0.5 V
3-125
Electrical Specifications
(Continued)(NOTE 3) (NOTE 4)
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Short Circuit Current los Vee = Max (Note 5), VOUT = GND -SO -85 -240 mA
(Note S)
Power Down Disable 10FF Vee = OV, VIN or VOUT S 4.5V
-
±100ItA
Input Hysteresis VH 150 mV
CAPACITANCE TA = 25°C, f = 1 MHz
Input Capacitance CIN VIN=OV 4.5 S pF
(Note 8)
Output Capacitance COUT VOUT=OV
-
5.5 8 pF(Note 8)
POWER SUPPLY SPECIFICATIONS
Quiescent Power ICC Vec= Max VIN=GND
-
0.1 10 I1ASupply Current or Vee
Quiescent Power ~Iee Vee = Max VIN = Vee - O.SV 2.0 30
ItA
Supply Current TIL (Note 9)
Inputs HIGH
Dynamic Power IceD Vee = Max, Outputs Open VIN=Vee
-
50 75JlAI
Supply OEx=GND VIN=GND MHz
(Note 10) One Bit Toggling
50% Duty Cycle
Total Power Supply Ie Vec = Max, Outputs Open VIN = Vee - O.SV O.S 2.3 mA
Current (Note 12) fl = 10MHz, 50% Duty Cycle VIN=GND OEx=GND
One Bit Toggling
Vee = Max, Outputs Open VIN = Vee - O.SV
-
2.1 4.7 mAfl = 2.5MHz, 50% Duty Cycle VIN=GND (Note 11)
OEx=GND 10 Bits Toggling
3-126
CD74LPT827
Switching Specifications Over Operating Range (NOTE 13)
(NOTE 14) CD74LPT16827A CD74LPT16827B CD74LPT16827C TEST (NOTE 15) (NOTE 15) (NOTE 15)
PARAMETER SYMBOL CONDITIONS MIN MAX MIN MAX MIN MAX UNITS
Propagation Delay tpLH, CL= 50pF 1.5 6.5 1.5 5.0 1.5 4.4 ns
DxxtoYx tpHL RL=500Q
Output Enable Time tpZH, 1.5 9.5 1.5 8.0 1.5 7.0 ns
OExtoYx tPZL
Output Disable Time tpHZ, 1.5 8.5 1.5 6.0 1.5 5.7 ns
(Note 16) tpLZ
()Ex to Yx NOTES:
3. For conditions shown as Max or Min, use appropriate value specified under Electrical Specifications for the applicable device type.
4. Typical values are at VCC = 3.3V, 25°C ambient and maximum loading.
5. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
6. This parameter is guaranteed but not tested.
7. VOH = VCC - 0.6V at rated current.
8. This parameter is determined by device characterization but is not production tested.
9. Per TIL driven input; all other inputs at VCC or GND.
10. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
11. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
12. Ie = laUIESCENT + IINPUTS + IDYNAMIC IC = Ice + Alce DHNT + ICCD (fcp/2 + flNI) Icc = Quiescent Current (lcCL,ICCH and ICCZ) AICC = Power Supply Current for a TIL High Input DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
IceD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCp = Clock Frequency for Register Devices (Zero for Non-Register Devices) tl = Input Frequency
NI = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.
13. Propagation Delays and Enable/Disable times are with VCC = 3.3V ±O.3V, normal range. For VCC = 2.7V, extended range, all Propaga-tion Delays and Enable/Disable times should be degraded by 20%.
14. See test circuit and wave forms.
15. Minimum limits are guaranteed but not tested on Propagation Delays.
16. This parameter is guaranteed but not production tested.
3-127
Test Circuits and Waveforms
NOTE:
17. Pulse Generator for All Pulses: Rate S 1.0MHz; loUT S 50Q;
tf. tr S 2.5ns.
FIGURE 1. TEST CIRCUIT
CONTROL INPUT
OUTPUT NORMALLY LOW
OUTPUT NORMALLY HIGH
FIGURE 2. ENABLE AND DISABLE TIMING
SWITCH POSITION
TEST SWITCH
tpLZ. tPZL. Open Drain 6V
tpHZ. tPZH GND
tpLH. tpHL Open
DEFINITIONS:
3-128
CL
=
Load capacitance. includes jig and probe capacitance.RT
=
Termination resistance. should be equal to loUT of the Pulse Generator.SAME PHASE INPUT TRANSmON
OUTPUT
OPPOSITE PHASE INPUT TRANSmON
, . - - " ' - : - - - 3V
~---1.5V ' - - - O V
~~~r+---VOH -1.5V --:,,-~_VOL
1 ' ' ' ' - - 3 V - # - - - - 1 . 5 V ' - - - ' - - - OV FIGURE 3. PROPAGATION DELAY