Snooping Protocol Examples

The following examples illustrate how snooping maintains cache coherency in a multiprocessor configuration. The examples assume that there are two MC88110/MC88410 nodes that share one common external system bus with main . memory. Each of the figures show a cache line within MC88II0-A, MC88410-A, MC88110-B, and MC88410-B, and the associated line address tags. The state of the cache line (invalid (lNV), shared-unmodified (SU), unmodified (EU), or exclusive-modified (EM» is also shown as well as the next state of the line as a result of bus transactions or snooping. Examples 1 and 3 only show one line in the primary data caches for simplicity. Example two shows both primary cache lines.

Examples 1 and 3 assume that the MC88410 is configured with a 32-byte line size.

Example 2 shows the MC88410 configured for a 64-byte cache line. Also, the starting address is shown as $0000. Address $0008 corresponds to double word I, address $0010 corresponds to double word 2, etc. Line read operations perform four consecutive double-word reads from memory addresses $0000, $0008, $0010, and $0018 to the cache line using the efficient burst mode transfer mechanism of the MC88410 with streaming to the MC88II0. Line copyback operations write (burst) the four double words from the secondary cache line back to memory.

For these examples, all addresses are assumed to be mapped as global, write-back, cache able, and not write-protected. Also, the primary caches are assumed to be operating in the three-state model since the SHD input signal of the MC88II0 is grounded. The secondary caches are assumed to be operating in the four-state model since the SHD input signal is connected to S_SSTATO (for more information about the four-state model, see 2.4.2 Lateral Coherency).

2.9.4.1 Example 1-Snoop Hit without Intent-to-Modify, PTAG Hit

This example illustrates the progression of events for the case of a snoop hit for a transaction without intent-to-modify. Figure 2-23 shows the caches in their initial state, with the cache lines invalidated in all locations and their contents unknown. This is the

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state of the data cache after reset, assuming that the system software has invalidated all the cache lines in both the primary and secondary caches.

MC88110- A PRIMARY

CACHE-A INV

I ???? I ? I ? I ? I ? I ? I ? I ? I ? I

MC88410-A SECONDARY

CACHE-A INV

I ???? I ? I ? I ? I ? I ? I ? I ? I ? I

$0000

$0004

$0008

$OOOC

$0010

$0014

$0018

$001C

MAIN MEMORY

MC88110- B PRIMARY

CACHE-8 INV

I ???? I? I ? I ? I ? I ? I ? I ? I ? I

MC88410- B SECONDARY

CACHE-8 INV

I ???? I? I ? I ? I ? I ? I ? I ? I ? I

Figure 2-23. Initial State - Example 1

Figure 2-24 shows MC88110-B performing a load word operation from location $0000.

There is a cache miss in both the primary and secondary caches, and MC88410-B reads a line from memory to fill the secondary cache line while streaming the data to MC88110-B.

MC88410-A monitors (snoops) the bus transaction, but does not find a match in the MTAG (a miss) since the entire data cache is marked as invalid. MC88410-B updates the state of the secondary cache line to exclusive-unmodified, and MC88110-B updates the state of the primary cache line to shared-unmodified.

MC88110- A PRIMARY

CACHE-A INV

MC88410-A SECONDARY

CACHE-A INV

I ???? I? I

I ? I ? I ? I ? I ? I ? I

$0000

$0004 1 - - - - 1

$0008

$OOOC '--_--'

$0010

$0014

$0018

$001C

MAIN MEMORY

MC88110- B

MC88410-B SECONDARY CACHE-B

Figure 2·24. MC88110 - B Load, Data Cache Miss

Figure 2-25 shows MC88110-A reading a word from address $0008, which misses for the selected cache line. A line fill operation is performed as before, with MC88410-A reading the line from memory and streaming the data to MC88110-A. MC88410-B snoops the global transaction and finds a tag match (a snoop hit). The state of the line changes to shared-unmodified in both secondary caches and remains shared-modified in primary cache A since both nodes have a copy of the data that is unmodified with respect to memory. Note that since the transaction is not intent-to-modify, MC88110-B is not informed of the snoop hit.

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MC88110 -A

MC88410-A SECONDARY CACHE-A

$0000

$0004

$0008

$OOOC

$0010

$0014

$0018

$001C H

MAIN MEMORY

MC88110- B PRIMARY

CACHE-B SU

I $0000 I AI BI

ci 01

pi

MC88410 - B SECONDARY

CACHE - B EU -. SU

I $0000 I AI BI

ci 01

pi

Figure 2-25. MC88110 - A Load, Data Cache Miss·

Figure 2-26 shows MC88110-B performing a store operation of a word to address $0000.

A cache hit occurs, and since the address was global, a processor invalidate transaction is performed. MC88410-B then performs a system bus invalidate transaction. The invalidate transaction notifies MC88410-A that its local copy of the line is no longer valid, so MC88410-A marks its cache line as invalid and performs a primary cache invalidate so that MC88110-A invalidates its line. When the invalidate transaction completes successfully, MC88410-B updates its secondary cache line and marks its line exclusive-modified. MC88110-B then updates the primary cache line with the new data and marks the line exclusive-modified.

Processor node B now has exclusive ownership of the entire line of data that is modified with respect to memory. The exclusive status guarantees processor node B that no other processor node on the bus can cache a valid copy of the line. All subsequent load and

store operations performed by MC88110-B that map to this line complete without accessing MC88410-B or the system bus. Note that although the copy of the line in MC88410-B is valid, the image of the line in the secondary cache is stale. This example shows that the exclusive-modified status in the secondary cache does not mean that the MC88410 has exclusive ownership of the line, but that the processor node has exclusive ownership of the line. This is also why the MC88410 must perform a processor invalidate cycle before copying a line that is marked exclusive-modified back to main memory.

MC88110- A

(Memory Image of the Line is Stale)

Figure 2·26. MC88110 - B Store, Data Cache Hit

(Secondary Cache Image of the Line is Stale)

Figure 2-27 shows MC88110-A attempting a load from location $0008. The transaction misses in both the primary and secondary caches because the lines in both cases are marked as invalid, which forces MC88410-A to perform a read-without-intent-to-modify transaction. MC88110-B snoops the access, recognizes that it has cached modified data requested by processor node A, and retries the line read operation by MC88410-A.

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MC88410-B then arbitrates for the processor bus and performs a primary cache invalidate transaction. The snoop hardware on MC88110-B then performs a snoop copyback, and invalidates the primary cache line (because the primary cache invalidate transaction is always intent-to-modify). The MC88410 updates the secondary cache line and is ready to perform its snoop copyback to main memory.

MC88110- A

~I ______________________________________________ ^~BUS~ ________________________________________ ^~I

$0000 A

(Memory Image of the Cache Line is Stale)

Figure 2·27. MC88110 - A Load, Cache Miss, Line Read Retried

Figure 2-28 shows MC88410-B copying back the exclusive-modified line to memory and marking the cache line as shared-unmodified (because the snooped transaction was not intent-to-modify). Since snoop copybacks are not global, no other processor nodes snoop the transaction.

MC88110-A MC88110- B

PRIMARY PRIMARY

CACHE-A INV CACHE-B INV