Processor Single-Beat Transactions

This section assumes that processor transactions hit in the secondary cache and are not propagated to the system interface. For information regarding'system bus transactions, refer to Section 5 System Bus Interface. For information regarding processor bus transactions and the effect of cache coherency considerations on data transfer, refer to Section 2 Secondary Cache Operation.

In Table 4-5, note that the P _UPAI-P_UPAO signals are not shown since they are always determined by the MC88110 memory management unit (MMU).

Note that since the Me signal of the MC88110 is not connected to the MC88410, all processor transactions (including invalidates) cause data to be transferred to the secondary cache. In the c~se of a primary cache invalidate transaction, the data is marked invalid in the main tag (MTAG) even though data is written to the secondary cache. The

P_INV signal is asserted by the MC88110 to indicate that the MC88410 should perform a system invalidate broadcast, if necessary, to maintain cache coherency.

The P_INV signal is asserted by the MC88410 to indicate to the MC88110 that it should invalidate its corresponding primary data cache line. The P_INV signal is asserted for all write transactions, locked read transactions, and allocate load transactions. .

4.4.3 Processor Single-Beat Transactions

Accesses that occur directly on the external bus independently of the data cache (regardless of a cache hit) cause single-beat transactions to occur. Transactions in Table 4-5 with P _'f.BST negated are single-beat transactions. All single-beat transactions have similar timing characteristics; the differences between the transactions are determined by the transfer attribute signals that are asserted/negated.

Figure 4-8 shows the relative timing of the data transfer signals during a single-beat transaction in the case of a secondary cache hit. Before a single-beat transaction begins, the MC88110 arbitrates for bus mastership, if it is not parked, and becomes the processor bus master.

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Figure 4-8. Single-Beat Transact~on - Fastest Case

In Figure 4-8, the processor drives the address signals with the physical address of the access off the rising edge of clock 1 and at the same time asserts the appropriate attribute and control signals for the type of single-beat transaction being performed. The MC88410 latches the address and control information on the rising edge of clock 2. During clock 2, the MC88410 decodes the access information, determines whether there is a hit or a miss in the secondary cache, and drives the appropriate RAM address and control signals to the MCM62110 array. The MC88410 keeps the P_TA signal negated for at least one clock cycle in order to allow sufficient time to process the transaction.

To indicate the status of the transaction to the processor, the MC88410 either asserts or negates P_TA. In the case of a cache hit, P_TA is asserted (clock 3 in Figure 4-8) two clocks after the address is driven on the processor address bus. If there is a cache miss, P _TA is negated until the clock following system bus data transfer termination.

While P_TA is negated, the processor waits and continuously drives the address (and data for write transactions) on the processor bus until P_TA is asserted. During the clock cycle after the assertion of P _TA, the address lines are three-stated and P _ABB is negated by the MC88110.

4.4.3.1 Processor Single-Beat Read Transaction

Single-beat read transactions include cache-inhibited accesses and MMU descriptor fetches that occur during table search operations. The P _INV signal is asserted only for locked (xmem) reads and allocate load transactions (which are intent-to-modify). During a single-beat read transaction, the MC88110 reads a byte, half word, word, or double word from the memory system.

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To perform a single-beat read transaction, the MC88110 first arbitrates for mastership of the processor bus if it is not the current bus master. The MC88110 then drives the address onto the address bus, asserts or negates the appropriate transfer attribute signals, and asserts P_TS as shown in Figure 4-9.

1) Set Rfii to Read 1) Decode Address and

2) Drive Address on A31-0 Transfer Attributes

3) AssertP _ABB 2) Tag Look up

4) Drive Size on TSIZ1-0 3) AssertP _PTA

5) NegateTBST 4) Negate PTE

6) Drive Transfer Attribute Signals 5) Negate P _ T A

7) Assert P _ TS 6) Drive Address on R_A16-0

7) Assert POE 8) Assert RWE7-Q

Figure 4-9. Single Beat Read Transaction Flow - Secondary Cache Hit

Once the MC88410 latches the address and drives it to the MCM62110 array, the MCM62110 array supplies the requested data on the appropriate 063-00 signals within the required setup and hold times while the MC88410 asserts P_TA. If the transaction had missed in the secondary cache, the MC88410 inserts wait states by negating P _TA until the data is available. For timing diagrams of transactions that miss in the secondary cache, refer to Section 5 System Bus Interface.

Figure 4-10 shows the relative timing for single-beat read transactions that hit in the secondary cache. The processor drives the address signals with the physical address of the access off the rising edge of clock 2 and at the same time asserts the appropriate attribute and control signals for the single-beat read transaction. The MC88410 latches the address and control information on the rising edge of clock 3 and asserts P _PTA (not

shown). The MC88410 always asserts P _PTA one clock after the processor asserts P _TS. In order to perform a cache tag lookup and to drive the RAM address and control signals to the MCM62110 array, the MC88410 inserts a wait state for one clock by negating P_TA. If a cache hit occurs, the data is transferred to the processor in clock cycle 4 and ^{P _T A} is asserted to indicate the end of the transaction. During a cache miss, P _TA is negated until the data is available from the system bus.

4 5

Figure 4-10. Single-Beat Read Hit Timing 4.4.3.2 Processor Single-Beat Write Transaction

Single-beat write transactions consist of cache-inhibited write transactions, write-through transactions, primary cache invalidate, and processor invalidate transactions. In the write-through mode, write transactions update external memory every time the primary cache line is modified. Write transactions that hit the secondary cache are written into it and to the system interface. A primary cache invalidate transaction occurs when there is a system bus write- or read-with-intent-to-modify which affects a line in the primary cache that is marked unmodified in the MC88110. Processor invalidate transactions occur when the MC88110 first writes to a primary cache line. Processor invalidate transactions always hit the secondary cache and leave the MC88410's line in a modified state (a system invalidate precedes the state change if necessary).

During a single-beat write transaction, the MC88110 transfers a byte, half word,word, or double word to the MC88410. To perform a single-beat write transaction, the MC88110 first becomes the processor bus master if it is not already the bus master. The MC88110

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then asserts P_TS, drives the address, and asserts or negates the appropriate attribute and control signals. All write transactions cause P _INV to be asserted ..

Once the MC88410 drives the address to the MCM62110 array, the MCM62110 latches the data from the appropriate D63-DO signals in the following clock. In the event of a secondary cache miss, the MC88410 inserts wait states by negating P _TA until the data is latched on the system bus. The MC88110 continues to drive the address and data on the processor bus until P_TA is asserted (or the transaction is otherwise terminated). Figure 4-11 shows the transaction flow for a single-beat write transaction.

1) Set PJW to WrRe 2) Drive Address on A31-AO 3) AssertP _ABB 4) Drive Size on TSIZ1-TSIZO 5) NegateP _ TBST

6) Drive Transfer Attribute Signals

7) Assert P _ TS Decode Address and Do a Cache

Looku~

AssertP _PTA

. 3) Drive RAM Address on R_A 16-0 . 4) AssertPIE and RWE7-0 .. 5) NegateP _ TA

Figure 4-11. Single-Beat Write Transaction Flow

Figure 4-12 shows the relative timing for single-beat write transactions. The processor drives the address signals with the physical address of the access off the rising edge of clock 2 and at the same time asserts the appropriate attribute and control signals for the single-beat write transaction. The MC88410 latches the address and control information on the rising edge of clock 3 and asserts P_PTA (not shown). The MC88410 always asserts

P _PTA one clock after the processor asserts P _TS. In order to perform a cache tag lookup and to drive the RAM address and control signals to the MCM62110 array, the MC88410

inserts a wait state for one clock by negating P_TA. When a secondary cache hit occurs, as shown in Figure 4-12, the data is written into the MCM62110 array in clock cycle 4, when

P_TA is asserted by the MC88410 to terminate the transaction. In the case of a secondary cache miss, the memory update policy determines if data is written into the secondary cache (see Section 2 Secondary Cache Operation).

2 3 4

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Figure 4-12. Single - Beat Write Hit Timing