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4.4 DATA TRANSFER MECHANISM
4.4.5 Processor Burst Transactions
Transactions in Table 4-5 with P _TBST asserted are burst transactions. Burst transactions perform the transfer of four double words between the processor and the secondary cache and/or the system bus.
Data transfers on the processor interface always start with the double··word address presented by the processor. For read miss line fills, this is the "critical word" address. As a result of critical-word-first ordering, the read miss line fill (or copyback) transaction always begins with the evenly~aligned double word containing the missed word (that is, critical-word-first), followed by the subsequent double word(s) in the cache line, if any.
If the double word containing the missed data does not correspond to the first double word in the cache line, the fill operation wraps around and then fills the double word(s) at the beginning of the line. Data is always transferred on the processor bus in critical-word-first order for burst transactions.
To begin a transaction, the processor drives the address of the critical word on the processor bus and asserts P _TBST to indicate a burst transaction. When the MC88410 detects that the transaction is a burst, it internally increments the address of the remaining double words to MCM62110 array. The incremented addresses provided by the processor bus are not used.
When the double-word data is guaranteed to meet the appropriate setup and hold times, the MC88410 asserts P _TA to terminate the beat. At this time, either the address is incremented to be the address for the next beat of the burst or if all four beats have completed successfully, the burst transaction is terminated.
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If the data cannot be supplied in the clock cycle after the address is sampled, P_TA is negated until the data is available. While P _TA is negated, the processor waits and continuously drives the address on the processor address bus until P_TA is asserted.
If the transaction terminates with an error, the actions of the processor depend on when the error is detected and the type of transaction being performed.
Figure 4-14 shows the relative timing of the data transfer signals during a burst transaction that hits in the secondary cache. Before a burst transaction begins, the processor arbitrates for the processor bus and becomes the bus master. The processor then drives the address signals with the physical address of the access in clock 1 and at the same time asserts the appropriate attribute and control signals for the type of burst transaction being performed.
In clock 2 the MC88410 continues to negate P_TA, determines whether the transaction hit in the secondary cache, and drives the address to MCM62110 array. In the case of a cache hit, the MCM62110 array latches or drives the data for the first beat of the burst during clock 3. The next three beats of the burst occur during subsequent clock cycles. To indicate the status of each of the four beats of the burst transaction to the processor, the MC88410 either asserts or negates the P_TA signal.
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.Figure 4·14. Burst Transaction· Fastest Case 4.4.5.1 Processor Burst Read Transaction
Figure 4-15 shows the transaction flow for a burst read transaction. During a burst read transaction, the MC88110 transfers four double words from a secondary cache line to the MC88110.
To perform a burst read transaction, the·MC88110 first arbitrates for mastership of the processor bus if it is not parked. The MC88110 then drives the address onto the bus, asserts or negates the appropriate transfer attribute signals, and asserts P _TS to signal the start of a new transaction. The MC88110 also asserts P_TBST to signal a burst transaction.
1) Set FWl to Read
2) Drive Address on P _A31·P _AO 3) AssertP ABB
4) AssertP _ TBST
5) Drive T..ransmr Attribute Signals 6) AssertP _ TS
1) Decode Address and Tag Lookup 2) AssertP _PTA
3) Drive RAM Address on R_A 16-0 4) AssertPOE
Acknowledge Valid Data Transfer AssertP _ TA
Increment Address Bits R_A 1-0
Figure 4·15. Burst Read Transaction Flow
The MC88410 decodes the address and transfer attribute signals and performs a cache tag lookup to determine if there is a secondary cache hit or miss. Then the MC88410 drives the address and control signals to the MCM62110 array and asserts P_PTA signal. The MC88410 always asserts P_PTA one clock after the processor asserts P_TS.
Once the MC88410 drives the address to the MCM62110 array, the MCM62110 drives the requested data on the appropriate 063-00 signals in the following clock if the transaction hits in the secondary cache. In the event of a secondary cache miss, the MC88410 inserts wait states by negating P _TA until the data is available. For timing diagrams of transactions that miss in the secondary cache, refer to Section 5 System Bus Interface.
The timing for a processor burst read transaction that hits in the secondary cache is shown in Figure 4-16. In clock 1, the processor begins the transaction by driving the address on the processor bus, asserting P _ABB, and asserting P _TS to signal a new transaction. The MC88110 negates P_R/W for the read transaction and asserts P_TBST signal to indicate a burst transaction. In clock 2, the MC88410 drives the appropriate address and control information to the MCM62110 array. The POE signal is asserted to enable data transfer from MCM62110 array to the processor. To perform a cache tag lookup and to drive the
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RAM address and control signals to the MCM62110 array, the MC88410 inserts a wait state in clock 2 by continuing to negate P _TA.
Since the transaction hits in the secondary cache, the MCM62110 array drives the first aligned double word on the data signals (p DATA)in clock 3 and the MC88410 asserts P_TA.
At the same time, the MC88410 increments the RAM address to the next double word and asserts RWE7-RWEO. During each of the following three clock cycles, data for the specified address is placed on the data bus and the address
is
incremented to reflect the address of the appropriate double word. The address, data, and control signals are three-stated in clock 7, and P _TA is negated to signal the end of the transaction.elK
Figure 4-16. Burst Read Hit Timing
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1-4.4.5.2 Processor Burst Write Transaction
During a burst write transaction, the MC88110 transfers four double words from a data cache line to memory.
To perform a burst write transaction, the MC88110 first arbitrates for mastership of the processor bus if the MC88110 is not parked. The MC88110 then drives the address onto the bus, drives the data on the appropriate 063-00 signals, asserts or negates the appropriate transfer attribute signals, and asserts P _TS to signal the start of a new transaction. The MC88110 also asserts P_TBST to signal a burst transaction. The P_INV
signal is asserted for all write transactions.
The MC88410 decodes the address and transfer attribute signals and performs a cache tag lookup to determine if there is a secondary cache hit. Then the MC88410 drives the address and control signals to the MCM62110 array and asserts P _PTA (not shown). The MC88410 always asserts P_PTA one clock after the processor asserts P_TS. The MCM62110 array latches the address and the data from the processor bus.
Once the MC88410 drives the address to the MCM62110 array, the MCM62110 latches the data from the appropriate 063-00 signals in the following clock. In the event of a secondary cache miss, the MC88410 inserts wait states by negating P _TA until the data is latched on the system bus. For timing diagrams of transactions that miss in the secondary cache, refer to Section 5 System Bus Interface. The MC88110 continues to drive the address and data on the processor bus until P_TA is asserted (or the transaction is terminated). Figure 4-17 shows the transaction flow for a burst write transaction.
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1) Set Rfii to Write 2) Drive Address on A31·AO 3) Assert P ABB 3) AssertP _ TBST
1) Decode Address and Tag Lookup 2) Assert P PT A_
5) Drive T.ran.sre.r Attribute Signals 6) AssertP _ TS
3) Drive R WE 7 -0, RAM Address on R_A16,:L
AssertPIE
Present Data
Figure 4·17. Burst Write Transaction Flow
The timing for a processor burst write transaction that hits in the secondary cache is shown in Figure 4-18. In clock I, the processor begins the transaction by driving the address on the processor bus, asserting P _ABB, and asserting P _TS to signal a new transaction. The MC88110 asserts P _R/w for the write transaction and asserts P _TBST
signal to indicate a burst transaction. The MC88110 also drives the data on the appropriate data signals (p DATA) in clock 1. In clock 2, the MC88410 drives the appropriate address and control information to the MCM62110 array. The PIE signal is asserted to enable data transfer from the processor to the MCM62110 array. To perform a cache tag lookup and to drive the RAM address and control signals to the MCM62110 array, the MC88410 inserts a wait state in clock 2 by continuing to negate P_TA.
Because the transaction hits in the secondary cache, the processor transfers the first aligned double word on the data bus in clock cycle 3 and the MC88410 acknowledges this by asserting P _TA. At the same time, the MC88410 increments the RAM address to the next double word. During each of the following three clock cycles, data for the specified address is transferred on the appropriate 063-':DO signals and the address is incremented to reflect the address of the appropriate double word. The address, data, and control signals are three-stated in clock 7, and P _TA is negated.
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Figure 4-18. Burst Write Hit Timing