Lateral Coherency

2.4.2 Lateral Coherency

The MC88410 uses the MT AG and system interface snooping to maintain data coherency between secondary caches and main memory according to the lateral coherency state machine. The MC88410 snoops all global traffic on the system address interface.

Alternate masters on the system interface use a wait-retry protocol to alert the interface master of potential coherency hazards.

The MC88410 cache state logic is implemented as a four-state design, but also supports a three-state model. The three-state model includes all of the states except the exclusive-unmodified state. When operating in the three-state model, all internal cache state transitions are visible on the external signals of the MC88410. In the four-state model, the transition from the exclusive-unmodified state to the exclusive-modified state for a write hit is not visible on the bus.

The distinction of whether the three- or four-state model is in use is determined by the status of the two shared input signals on the system bus interface (SHD and TSHD). Other snooping MC88410s on the bus should drive the SHD signal with their snoop hit status output (S_SSTATO). Systems with distant snoopers can assert TSHD as late as the first S_TA.

For more information about the timing for the SHD and TSHD signals, refer to Section 5 System Bus Interface. Systems implementing a three-state cache model simply keep the

SHD signal asserted and force all line fills to be marked as shared-unmodified. Note that during line fills for write misses in write-back mode, the ^SHD signal is ignored (i.e., write miss line fills are always marked as exclusive-modified).

State transition diagrams for the data cache in the four-state model are shown in Figures 2-8 and 2-9 and described in the following paragraphs. Figure 2-8 shows the state transition diagram for the cache operating in write-back mode, and Figure 2-9 shows the state transition diagram for the cache operating in write-through mode. State transitions for the cache in the three-state model are shown in Figure 2-10. All other operations that are not explicitly shown in these diagrams do not affect the cache state.

In the following diagrams, state transitions labeled as "shared" (for example, shared read miss) imply that the SHD or TSHD input signals to the MC88410 are asserted at the appropriate time during the line fill operation.' Transitions labeled as "exclusive~' imply that the SHD and TSHD input signals are negated during the line fill.

Figure 2-8 shows all state transitions possible for the secondary cache in write-back mode for the four-state model. A line can change state due to a cache miss. Replacing a cache line with a line from main memory is referred to as replacement. For any initial state, an exclusive read miss with replacement changes the line state to exclusive-unmodified, a shared read miss with replacement changes the line state to shared-unmodified, and a write miss with replacement or a read miss with intent-to-modify changes the line state to exclusive-modified. In a multiprocessor system a snoop hit on a read changes the line state of the snooping processor node to shared-unmodified (after a copyback of the data, if modified). A snoop hit on a write- or read-with-intent-to-modify changes line state of the snooping processor to invalid (after a copyback of the data, if modified). When the MC88110 performs a processor invalidate transaction to an unmodified line, the line state

changes to exclusive-modified. If an exclusive-modified line is flushed, the line state changes to unmodified. Finally, if there is a locked read hit to a shared-unmodified line, the line state changes to exclusive-unmodified (after a system invalidate transaction).

Write operations in write-through mode leave the cache state unaffected. Figure 2-9 shows all state transitions possible for the secondary cache when in write-through mode.

The exclusive-unmodified state cannot be reached in write-through mode. If a cache line is already in either of the exclusive states when write-through mode is selected, the line does not change state while in write-through mode. This does not. cause coherency problems, but if the mode is changed back to write-back, some data may be copied back to memory which is already consistent with the line in the data cache.

C~e-i1hib~ed hft, or snoop hit with intenHo-modify

Write miss or lead miss with intent-to-modify

(w~h replacement)

Shared lead miss (whh replacement) Invalidate command

Write hit or processor invalidate Exclusive lead miss

(w~h replacement) or flush command (whh oopyback)

Snoop hit, read

Exclusive lead miss ' (whh replacement)

Figure 2-8. Secondary Cache States in Write-Back Mode

IFJ

Slared read miss (with replacement)

Snoop hit on wrtte or

read-with~ntenHoillodify, or invalidate command

Figure 2-9. Secondary Cache States in Write-Through Mode

Figure 2-10 shows all possible state transitions for the secondary cache in the three-state model. The three-state model does not include the exclusive-unmodified state.

SlIIred read niss (wtth replacement)

Invalidate command, cache-inhibited hit, or snoop hit with

intent·to-modify

Invalidate command, cache-inhibited hit, or snoop hit with

intenHo-modify

Shared read niss (with replacement) or flush command

Figure 2-10. Secondary Cache States with Three-State Model

For the three-state model, any read miss line fill that is not intent-to-modify puts the line in the shared-unmodified state. Any line fill that is intent-to-modify puts the line in the exclusive-modified state. When the MC88110 performs a processor invalidate transaction to a shared-unmodified line, the line state changes to exclusive-modified. If a snooping system bus master (MC88410 or MC88110) performs a snoop copyback transaction, then the cache line of the snooping bus master changes state to either shared-unmodified (for a read) or invalid (for a write- or a read-with-intent-to-modify) depending on what caused , the snoop copyback.

There are potential benefits to both the three-state and four-state models. The three-state model is useful because all internal state transitions are visible on the system bus. (Note that the primary cache in an MC88110/MC88410 system always uses the three-state'model because the SHD input to the MC88110 is grounded.) However, the three-state implementation can cause lower performance than the four-state implementation. In the three-state implementation, the exclusive-unmodified state does not exist; therefore, all data is read in as shared-unmodified. A write hit to shared-unmodified data causes the snooping bus master to perform an system invalidate transaction on the system bus. If the data had been read as exclusive-unmodified (as in the four-state model), then a write hit would simply change the state of the data to be exclusive-modified, and no system bus traffic would occur.