BURST ORDERING AND STREAMING - 2.1.2 1 Mbyte with 64-Byte Line Size Configuration

2.1.2 1 Mbyte with 64-Byte Line Size Configuration

2.6 BURST ORDERING AND STREAMING

The MC88410 provides burst data transfers across both the processor and system interfaces. Transfers across the processor interface always start with the double word presented by the processor and continue with the subsequent double word(s) in the line.

If the first double word is not the first double word in the line, the fill wraps around and fills the double word(s) at the beginning of the line. The MC88410 increments the address internally and sequences the MCM62110 array; the addresses incremented by the processor are not used.

The order of burst addressing on the system interface is programmable at reset. The two options are zero-word-first and critical-word-first. With critical-.word-first operation, the burst transfer on the system interface starts with the same double word as the burst transfer on the processor interface and continues with the subsequent double word(s) in the line, wrapping around if necessary. With zero-word-first ordering, the bursts on the system interface always start with double word zero. This ordering applies to both . secondary cache line fills and secondary cache snoop copyback transactions. Replacement copyback transactions always start with word zero. The MC88410 provides all addresses (four or eight) for burst operations on the system interface.

The MC88410 uses data streaming to reduce the penalty seen by the processor on secondary cache misses. With data streaming, data is written to the processor bus for the primary cache line fill as it is being written into the secondary cache from memory. Data streaming is straightforward for configurations with 32-byte secondary cache line size and

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critical-word-first system ordering. In this case, the data from each of the four transfers is written to both the secondary and primary caches. Note that the data is valid on the processor bus one clock after it is written to or read by the secondary cache. For information on the streaming timing see Section 5 System Bus Interface. Upon transfer of the last word to the primary cache, the operation is completed. An example of this is shown in Figure 2-11.

01 PRIMARY CACHE 01 02 PRIMARY CACHE

01 SECONDARY CACHE 01 02 SECONDARY CACHE

FIRST TRANSACTION SECOND TRANSACTION

1.-_--'-_0_1--"'_0_2--11...-_03---.11 PRIMARY CACHE 00 01 02 03 PRIMARY CACHE

1.-_--'-_0_1--"' _ _ 02--11...-_03---.11 SECONDARY CACHE 00 01 02 03 SECONDARY CACHE

THIRD TRANSACTION FOURTH TRANSACTION

Figure 2-11. Streaming with 32-Byte Secondary Cache Line and Critical-Word-First

Data streaming is more complex when the MC88410 is configured to have 64-byte secondary cache line sizes and/or zero-word-first system ordering. For example, when the system ordering is changed to zero-word-first, the secondary cache line is filled starting at word zero, regardless of which double word contains the critical information.

As the secondary cache line fill continues, streaming begins when the critical word from' the processor is reached. Upon completion of the secondary cache line fill, the MC88410 wraps around and completes the burst transaction to the processor.

Bus errors detected on the system bus during streaming must be passed to the processor bus. For configurations involving the 64-byte line size, if the critical word is the first word of the line, the entire primary cache Hne could be' streamed to the processor before the secondary fill has completed. However, if a bus error occurs on the secondary cache line fill after the primary cache line fill has completed, then there would be a valid primary line that was never loaded in the secondary cache violating the inclusion policy. To prevent this situation, the MC88410 does not complete the last transfer of the primary cache line fill until the secondary line has completed its line fill.

Figure 2-12 shows an example of when the critical double word is the second one in the line. In the first transfer, the data for the first double word is read into the secondary cache lines. For the three subsequent transfers, the data is read into the secondary cache line and streamed to the processor bus and the primary cache line. Upon successful

completion of the secondary cache line fill, the MC88410 must complete the primary cache line fill by wrapping around and writing the first double word on the processor bus.

PRIMARY CACHE 01

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PRIMARY CACHE

. 00 SECONDARY CACHE 00 01

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SECONDARY CACHE

FIRST TRANSACTION SECOND TRANSACTION

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⁰¹ ⁰² PRIMARY CACHE 01

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00 01 02 SECONDARY CACHE 00 01

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THIRD TRANSACTION FOURTH TRANSACTION

00 01

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00 01

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⁰² ⁰³ SECONDARY CACHE FIFTH TRANSACTION

Figure 2-12. Streaming with 32-Byte Secondary Cache Line and Zero-Word-First

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Another possible configuration is with 64-byte secondary cache lines and critical-word-first operation on the system bus. In this case, the critical double word is the critical-word-first transaction on the system bus, and the data is streamed to the processor bus during the transaction. The data continues to be streamed for each of the double words on the first half of the secondary cache line. While the second half of th"e secondary cache line is being read, the MC88410 inserts wait states on the processor bus. When the secondary cache line fill wraps around, the data streaming continues until the end of the line fill.

Figure 2-13 shows an example of when the critical double-word is the second one in the line. In the first transfer, the critical double word is read into the secondary cache line and streamed to the processor. The data for the subsequent two transfers is also read into the secondary cache and streamed to the processor. For the next four transfers, however, the data is read into the secondary cache while the MC88410 inserts wait states to the processor. When the secondary cache line fill wraps around to complete, data streaming resumes for the last double-word transfer.

Finally, the MC88410 could be operating with 64-byte secondary cache lines and zero-word-first operation on the system bus. In this case, the first double word is the first transaction on the system bus. The secondary cache line fill continues, and streaming begins when the critical word from the processor is reached. During the four double-word transfers for the second half of the secondary cache line, streaming is discontinued and the MC88410 inserts wait states on the processor bus. Upon completion of the secondary cache line fill, the MC88410 wraps around and completes the burst to the processor.

Figure 2-14 shows an example of when the critical double word is the second one in the line. In the first transfer for this case, the data for the first double word is read into the secondary cache lines. For the three subsequent transfers, the data is· read into the secondary cache line and streamed to the processor bus and the primary cache line.

During the remainder of the secondary cache line fill, the processor bus waits. Upon successful completion of the secondary cache line fill, the MC88410 must complete the primary cache line fill by wrapping around and writing the first double word on the processor bus.

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PRIMARY CACHE

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SECONDARY CACHE

FIRST TRANSACTION

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PRIMARY CACHE

01 02 SECONDARY CACHE

SECOND TRANSACTION

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PRIMARY CACHE

SECONDARY CACHE

FIRST TRANSACTION

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PRIMARY CACHE

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SECONDARY CACHE

SECONDARY CACHE

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Figure 2-14b. Streaming with 64 Byte Secondary Cache Line and Zero-Word-First

Dans le document MC88410 Secondary Cache Controller Userls Manual ®MOTOROLA (Page 50-57)