Processor Transfer Attribute Signals

The MC88410 processor transfer attribute signals differ from the MC88I10 by the absence of the ^MC signal. The timing for each of the transfer attribute signals is the same as the timing for the address bus signals, except during a locked transaction. Since the MC88410 parks the MC88II0 (p _BG asserted) between the two transactions of a locked transaction, the transfer attribute signals remain asserted during both transactions.

Processor ReadlWrite (P _RlW)

The P _R/W signal indicates whether the transaction is a read (p _R/w high) or a write ~

(P_R/W low) transaction. The ^P_R/W signal is an input when the MC88II0 drives an ~ address and an output only during a primary cache invalidate transaction (see 2.4 Cache

Coherency). It is three-stated at all other times.

Processor Lock (P_LK)

The MC88II0 drives the P_LK signal to indicate that an access is part of an atomic data-access sequence. The MC88II0 asserts the P_LK signal during locked transactions only.

During the execution of the locked transaction, the MC88II0 asserts the P_LK signal for both the read and write portions of the locked transaction. The P _LK signal is asserted to indicate that the bus arbitration circuitry should not allow another bus master to alter the data that the locked transaction accesses between the read and write transactions.

The MC88410 drives the S_LK signal to the system bus in response to the MC88II0 assertion of the P _LK signal. The state of P _LK determines the status of the S_LK signal.

Processor Cache-Inhibit

(P _ C

The P_CI signal indicates that the data will not be written into the MC88110 data cache.

For single-beat transactions, xmem transactions, and touch and allocate load transactions, the P_CI signal reflects the value of the CI bit in the address translation cache entry of the MC88II0. For all other transactions, the P_CI signal is negated.

The P _CI input signal causes the MC88410 to treat the current transaction as cache-inhibited. If the transaction hits in the secondary cache tags, the secondary cache line is flushed and invalidated before the access proceeds.

Processor Write-Through

(P _ W T)

The P _ WT input signal determines the memory update policy of the secondary cache. See Section 2 Secondary Cache Operation for more information.

Processor User Page Attributes (P _UPA1-P _UPAO)

The P_UPAI and P_UPAO input signals reflect the user attribute bits in the ATC entry of the MC88110. During MC88110 copyback operations, these signals are negated. The signals are received from the MC88110 and passed to the system interface for all transactions that require system bus interface mastership.

Processor Transfer Burst (P _ TBST)

The P _TBST signal indicates whether the transaction is single-beat or burst. It is an input when the MC88110 is driving an address and an output during a primary cache invalidate transaction. It is three-stated at all other times. When the P _TBST signal is asserted by the MC88110, the transaction is an eight-word burst. If it is negated, the transaction is a single-beat transaction and the size of the data to be transferred is encoded in the P _TSIZl-P_TSIZO signals. Note that P_TBST is ignored as an input if P_CI is asserted. The MC88410 asserts the ^{P _TBST} signal for a primary cache DMA invalidate transaction and negates it for a primary cache invalidate transaction.

Processor Transfer Size (P _ TSIZ1-P _ TSIZO)

The ^{P _TSIZI} and ^{P _TSIZO} signals indicate the size of the requested data transfer as shown in Table 3-3. All transfers are aligned to their respective size boundaries. The P_TSIZl-P _TSIZO signals may be used along with P _A2-P _AO to determine which portion of the data bus contains valid data for a write transaction or which portion of the bus should contain valid data for a read transaction. Note that the P_TSIZI-P_TSIZO signals indicate the size of the requested data transfer independent of the value of P _TBST, so it is possible for the processor transfer size signals to indicate a byte, half word, or word transfer when the

P _TBST signal is asserted. Therefore, if the P _TBST signal is asserted, the MC88410 transfers double words regardless of the P _TSIZI-P _TSIZO encoding.

Table 3-3. Processor Transfer Size Signal Encoding

P _ TSIZ1-P _ TSIZO Transfer Size 00 Double word (64 bits) 01 Word (32 bits) 1 0 Half word (16 bits) 1 1 Byte (8 bits)

Processor Transfer Code

(P _ TC3-P _ TCO)

The P _Tc3-P _TCO signals provide supplemental information about the corresponding address. The transfer code signals are encoded as shown in Table 3-4.

Table 3-4. Processor Transfer Code Signal Encoding

P_TC3-P_TCO Transfer Code

0000 Reserved

0001 User data access

0010 User touch, flush, or allocate access 0011 Data MMU table search operation 0100 Replacement copyback 0101 Supervisor data access

011 0 Supervisor touch, flush, or allocate access 01 1 1 Snoop copyback operation

1000 Reserved

1001 . User instruction access 101 0 Reserved

1 0 1 1 Instruction MMU table search operation 1 100 Reserved

1 1 0 1 Supervisor instruction access 1 1 1 0 Reserved

1 1 1 1 Reserved

Processor Invalidate (P _IN V)

When asserted by the MC88410, the P _INV output signal indicates that the MC88110 should invalidate the cache line on a snoop hit. If the snoop hit is to a modified primary cache line, the line is copied back before being invalidated. This signal is an input when the MC88110 is driving an address and an output when the MC88410 performs a primary cache invalidate transaction to the MC88110. It is three-stated at all other times.

Processor Global (P _GBl)

The processor address bus master asserts the ^{P _ GBL} signal to indicate that the transaction in progress is marked as "global." The ^{P _GBL} signal reflects the value specified for the memory reference in the corresponding MC88110 memory management unit. The MC88410 asserts the ^{P _GBL} signal during a primary cache invalidate transaction, so the MC88110 snoops on the address being driven. When the MC88110 is driving the processor address bus, the P_GBL signal is an input to the MC88410.

Processor Cache Line (P _Cl)

The P_CL input signal indicates which line in the MC88110 cache is involved in the current data transfer as shown in Table 3-5.

E

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Table 3-5. Processor Cache Line Signal

P_CL Cache Line

0 Line 0

1 Line 1